HiFive Unmatched Rev B UART issues

[alnyannn]

Hi all,

I'm trying to port my OS to SiFive HiFive Unmatched Rev B board and I'm having issues with UART interrupts.
The Tx path (polling) works fine and the device transmits bytes as expected, but in the Rx path, once I enable Rx watermark interrupt, I keep getting a constant stream of interrupts, with the Rx FIFO containing exactly 8 0x00 bytes. This does not occur if I try debugging the issue by polling the Rx in the init code without enabling the Rx IRQ.

My init sequence looks like follows:

• Get the UART's input clock rate (assumed enabled, entering from u-boot)

• Disable Tx/Rx by writing zeroes to TXCTRL/RXCTRL

• Configure baud rate by calculating divisor and writing to the DIV register

• Enable the Tx path by writing TXEN to TXCTRL, also set TXCNT = 3 for Tx watermark

• Drain the Rx FIFO by reading RXDATA until bit 31 becomes 1

• Register the UART with the system as a terminal device

• Register the IRQ in the handler, enable it in the PLIC

• RXCTRL = RXEN | RXCNT(0)

• IE = RXWM

After that, once interrupts are enabled globally, I start getting constant IRQs from the UART, and reading the FIFO fully in a loop returns exactly 8 (FIFO size) zero bytes. This is interrupted by 1-byte FIFO interrupt when I do actually send data to the board.

It seems I'm initializing the UART in the same way Linux/OpenBSD does, maybe I should look somewhere else (PLIC code?) for the cause? Maybe someone worked with this board and has any ideas?

[Octocontrabass]

When you receive the interrupt, do you read the UART registers to verify that the UART raised the interrupt?

[alnyannn]

Managed to solve the issue, the problem was quite simple: it wasn't the UART I was looking at raising the IRQs (the UART in question behaved well in fact), it was the second UART which I enabled when walking the device tree which was. The second UART had hanging Rx line, which caused the endless interrupts I presume