Hi there,
Can anybody help figure out these problems please.
Consider a data cache of size 128 bytes with a line (block) size of 16 bytes. The cache implements LRU and write back policy. On a write miss, the corresponding block is loaded into cache before the write operation. The addresses from the CPU are 12 bits long.
a) What will the (minimum) tag size be, in bits, if the cache is:
i) direct mapped
ii) fully associative
iii) 4-way set associative
b) Let the cache be 2-way set associative, with the following initial configuration (the * indicates which cache entry in each set was last accessed):
Tag (in hex) Set No. Valid Dirty
32 0 0 0
1F 0* 1 1
11 1* 1 1
33 1 1 0
0D 2* 0 0
11 2 0 0
07 3 0 0
3F 3* 0 0
If the next few data access were to the following addresses (in hex) in order :
R: 0x894
R: 0x22C
W: 0xCDF
R: 0x9C5
R: 0x01D
W: 0x77B
where R stands for read and W for write access, what is the final configuration of the cache, in terms of the above table. Use LRU as the replacement policy.
Thanks in Advance,
Maguru