Paging: self mapping

[Whatever5k]

I mapped the page directory into itself like this:

Code: Select all

extern addr_t *pdir;

pdir[1023] = pdir | 0x003;

This means that I can access the page directory at address (4GB - 4MB), right? So I use two macros for getting the PTE and PDE of a virtual address. But when I try to access the PDE, I get a page fault:

Code: Select all

#define PG_TABLE_SIZE 4096
#define PTE_SIZE 4
#define PG_DIR_START(0xFFFFFFFF - 0x400000) /* 4GB - 4MB */
#define ADDR_TO_PDE(virt) (PG_DIR_START + (virt >> 22) * PG_TABLE_SIZE)
#define ADDR_TO_PTE(virt) (PG_DIR_START + ((virt >> 12) &0xFFFFF) * PTE_SIZE)

void foo(addr_t virt)
{
  addr_t *pde;

  pde = (addr_t*) ADDR_TO_PDE(virt);
  if ((*pde & IS_PRESENT) == 0) /* that's where I get the page fault */
     ...
 ...
}

Any idea what might be wrong?

[Pype.Clicker]

did you flush the Translation Lookaside Buffers after you set up your page directory entries ?

i think your "PDE" macro is wrong.

*pde(virt) should refer to the page directory entry for VIRT, right ? this is (imho) located at PG_DIR_START + 1023*PG_TABLE_SIZE + (virt>>22)*PTE_SIZE, not where you set it

[Whatever5k]

did you flush the Translation Lookaside Buffers after you set up your page directory entries ?

Not really...how would I do this, how would I flush the whole TLB...I saw different ways...which is the right and common one?

*pde(virt) should refer to the page directory entry for VIRT, right ?

Well, it should return the virtual address of the PDE, yes...

[Whatever5k]

Alright, I flush the TLB by moving cr3 to eax and eax back to cr3...
Now after setting up the self mapping and enabling paging, I flush the TLB...but it still doesn't work...neither with your version of ADDR_TO_PDE