Exception handler and Paging?

[amirsadig]

hi,
I have a question. imagine we work on user mode and we use for each process a page directory which different from the kernel page directory. what does the cpu when an Exception occure?
what I know , it look in IDT to know if it is interrupt gate or task gate ..., suppose we have interrupt gate which include the code selector for the kernel and the offset of our exception handler. after cpu got the code selector, it know now our code segment but because paging is enable it translate the address with its MMU, which read the cr3, which before include the page directory of the user process. so it point to the wrong page.
how it load the write page directory?
if there is wrong with my description, please right me!

[amirsadig]

hey,
Another question.
after initializing the page directory, I mark the page directories, which we have not used it as unused. but what happend when I want to update the page directory, is cpu let me change the content of the page directory , when their physical address is not allocated.
you know after enabling paging all address will be translated in three phase.

for examble :
if my page directory start at 0x11000 and only the first entry marked as present. that know only 4 MB of memory could be accessed. ok now I want mark the second it as present.how could I do that ?

[Pype.Clicker]

The code for exceptions handling should either be present in every address spaces, or the exception should have a "task gate" entry for it and that task should have a PDBR value that maps an address space where handling is possible.

Also, you should make sure that your page directory (at least) is mapped in every address space -- and maybe also have a self-referencing entry in the directory (so that a 4MB slot of your address space is mapping every page table.

This will let you update page tables and directories easier...
(of course, page directory and page tables should not be modifiable from user mode

[amirsadig]

did you know how linux do that? what I know - from the book "understanding the linux kernel" - that linux use interrupt gate for exception handlers. and the handler code is saved in the kernel code semgment, which has its own address, and user address space does not include the kernel code address.

[Pype.Clicker]

every process in Linux has an address space split in 2 segments : The user-level segment (usually mapping 0000000 .. BFFFFFFF) and the kernel segment (mapping the whole memory, but only C0000000 .. FFFFFFFF is for the kernel itself).

The kernel is using the highest pages of every address space, so even if the page fault handler is not in accessible from the user mode, when an exception occurs, the interrupt trap redirect the execution to the kernel segment with the right handler address ...

So no problem ... i think you're overcomplicating things...