Paging and memory protection

[drizzt]

I need some suggestions about paging and memory protection...

When I enable paging I would like that all tasks have their virtual space and thir PDEs and PTEs.
When an interrupt occurs while a user task is running I would like to call the interrupt handler managed by the kernel...
But the interrupt handler is located in the kernel space, thus when an interrupt occurs I should update the CR3 with the page directory base address of the kernel.

Well... if I define all my IDT entries with a TASK GATE, automatically a task switch occurs when an interrupt or exception is generated, so the CR3 is automatically updated... but AFAIK this takes a lot of time, because the context switches save a lot of data

Another way could be to map the kernel space in every task address space, so when an exception or an interrupt occurs the address in the IDT should be generated correctly without perform a task switch, but what about memory protection for the kernel space?!

What do you think?! Can you suggest me a better way?

[pskyboy]

Mapping the address space into every app, Im suprised you don't map the address space into every app as this is pretty standard and is donw for other reasons as well. You need it there so that any kernel functions can be called by the app.

If you do it your way you will have to make a task switch on every call into the kernel. Im also not sure how a call is linked into an application if the kernel isn't in the address space and would be interested if you could enlighten me here.

Peter

[Slasher]

to protect the memory space, any page that is mapped into the PDE for the kernel should have its U/S bit marked as S (superviso, by setting it to 0 (I think))so no code in ring 3 can access that page. its explained in the Intel Docs

[drizzt]

Im also not sure how a call is linked into an application if the kernel isn't in the address space and would be interested if you could enlighten me here.

for example if you load the kernel in memory below 1GB and define user task selectors with base address >1GB
(I'm speaking about virtual addresses, with paging you can do everything you want ).

Then you can define all entries in the IDT via interrupt gate using kernel selecors (0-based) to access the kernel space... but when the user task is running the kernel is not in the address space of the task...

I dunno if it is what you intended before...

[Slasher]

Easiest way of calling kernel code is through interrupts.
ie in your idt int 0x40 could be dedicated to system calls, and you can provide C wrapper functions that accept parameters from the caller,places them in registers and issues the int 0x40.

[drizzt]

it is just what i meant... I think this is the best way to communicate between tasks and kernel and preserve mem protection... but what's the best way to map & allocate kernel and user space?

[Slasher]

when the kernel starts, setup its heap by allocating say 4mb(physical memory) and mapping it to the bottom of the PDT. when the malloc function is called you can check to see if the running process is a kernel or user app. if kernel then set the new page table entry to be mapped as SUPERIVISOR(see above post) else its USER

[drizzt]

yes i know... but my doubts are others.

For example if your kernel code is loaded from virtual address 0xC0000000 (3GB) to 0xD0000000(3GB+256MB), every user tasks should have their virtual addresses from 0xC0000000 to 0xD0000000 mapped in the physical address of the kernel (obviously mapped as supervisor page).
That's right?

[Slasher]

Thats Right!