g++ Problem with Pointer Size

[sebihepp]

Hi guys,

I have a problem with my kernel code. I switched from c to c++ and get the compile error: conversion to uin32_t from Struct* looses precision
I found out, that this should be related to gcc using 64bit pointers. But hey, I am programming a 32bit one. I tried -32 but that leads to an error, that the linker cannot read the object files. Then I tried -march=486 and this leads to another error: This architecture doesn't support X86_64
This doesn't happen with gcc and c as language. I don't know, what I should do now... I have a totally black out.

Best regards
Sebi

[madanra]

Are you using a cross compiler?

[xenos]

http://wiki.osdev.org/Why_do_I_need_a_C ... r_Compiler

[sebihepp]

I just figured it our too. All my cpp files are processed using the normal compiler (g++) But why? In my makefile I explicitely call i686-elf-g++. Are those + signs the problem?

Content of my makefile:

Code: Select all

AS = i686-elf-as
CC = i686-elf-gcc
CPP = i686-elf-g++

CFLAGS = -c -ffreestanding -nostdlib -O2 -Wall -Wextra -std=gnu99 -I../../include
CPPFLAGS = -c -ffreestanding -nostdlib -O2 -Wall -Wextra -fno-exceptions -fno-rtti -I../../include
LFLAGS = -T linker.ld -ffreestanding -O2 -nostdlib -lgcc


OUTPUT = heidelberg.bin
KERNEL_OBJECTS = boot.o main.o multiboot.o paging.o
OBJECTS = $(KERNEL_OBJECTS)


.PHONY: all
.PHONY: clean

all: $(OUTPUT)

$(OUTPUT): $(OBJECTS)
	$(CC) $(LFLAGS) -o $@ $(OBJECTS)

%.o: %.s
	$(AS) -o $@ $<

%.o: %.c
	$(CC) $(CFLAGS) -o $@ $<

%o: %.cpp
	$(CPP) $(CPPFLAGS) -o $@ $<
	
clean:
	rm *.o $(OUTPUT)
	

[madanra]

I don't know if this is related to your problem, but I noticed you're linking with $(CC):

Code: Select all

$(OUTPUT): $(OBJECTS)
   $(CC) $(LFLAGS) -o $@ $(OBJECTS)

Should this be $(CPP), given some of the object files are C++?

[Roman]

Code: Select all

%o: %.cpp

[sebihepp]

Code: Select all

%o: %.cpp

Yeah, that was the problem. Thank you very much. I think I would have been spent another few weeks, until I had seen this.

I don't know if this is related to your problem, but I noticed you're linking with $(CC):

Code: Select all

$(OUTPUT): $(OBJECTS)
   $(CC) $(LFLAGS) -o $@ $(OBJECTS)

Should this be $(CPP), given some of the object files are C++?

This step is only the linking, so compiling is already done. That's why I use normal gcc. I've read in the wiki, that you shouldn't use ld, but gcc, because gcc is doing some more things that could be required.

[xenos]

Further, it should not be CPP / CPPFLAGS - that would be the preprocessor. Use CXX / CXXFLAGS for the C++ compiler.

[Roman]

You also shouldn't define rules for *.c and *.cpp files. Just set CC, CXX, CFLAGS, CXXFLAGS (C++ compiler flags) and CPPFLAGS (preprocessor flags, both C and C++).

[sebihepp]

You also shouldn't define rules for *.c and *.cpp files. Just set CC, CXX, CFLAGS, CXXFLAGS (C++ compiler flags) and CPPFLAGS (preprocessor flags, both C and C++).

Well, how do I know then, when to call CC and when CXX?

Edit: Okay, I just found a website about predefined implicit rules in make. So I don't need them, just define CC, CXX, etc. and use rules to link, clean, and so on...

Further, it should not be CPP / CPPFLAGS - that would be the preprocessor. Use CXX / CXXFLAGS for the C++ compiler.

Thanks, One more thing I have learned.