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Hi everybody! ;D

I'm working on an OS project with a friend. At this point we need to implement new interrupt handlers. It seems that these are stored in the IDT. Can somone explain:
1. Where (in memory) are the IDT located?
2. What is the relation between interrupts (INT's) and IRQ's?
3. What is an interrupt gate, and does it some way relate to I/O ports?
4. I've found some code examples that look like this:

outb(0x20, 0x11); /* Start init of controller 0, require 4 bytes */
outb(0x21, IRQ_START); /* IRQ 0-7 use vectors 0x20-0x27 (32-39) */
outb(0x21, 0x04); /* Slave controller on IRQ 2 */
outb(0x21, 0x01); /* Normal EOI nonbuffered, 80x86 mode */
outb(0x21, 0xfb); /* Disable int 0-7, enable int 2 */

The people I hope to receive answers from, do definitely know what this code does. Unfortunately I dont, although I know that what this code does, is to initialise the first PIC on a Pentium machine. I also know that the first operand in these instructions (20 and 21) are addresses of some kind (I/O port addresses?) that points to the PIC0, and that the corresp. addresses to PIC1 are a0/a1. What I would like to know, however, is WHY these addresses, what is on address 10 or 6f for instance?

Is there possibly some good reference on this somewhere on the web?
I have downloaded the 3 volumes of Intel's reference guide, they are very exhaustive, I have still not found an answer to these questions. ???

I'd love some help

Greetings,
Marius :-*

Marius wrote: Hi everybody! ;D

Hi, Marius, welcome on board

First of all, i suggest you to head yourself to the .:QuickLinkz:. from where you'll find a (quick) link to Bona Fide OsDev. This website as a large quantity of valuable tutorial, including some on the IDT, PIC and other interrupt-related stuff.

It seems that these are stored in the IDT. Can somone explain:
1. Where (in memory) are the IDT located?

You (or your friend) are the one who will decide this, by the mean of the IDTRegister ... Basically, you prepare a 6 bytes area where you'll store the size and the base linear address of the IDT and then you load the IDTR with the content of that memory using the lidt instruction.

2. What is the relationship between interrupts (INT's) and IRQ's?

An IRQ is an Interrupt ReQuest coming from some hardware. All the IRQs are collected by a single chip called the Programmable Interrupt Controller (aka. i8259a -- don't look for it on your motherboard: it has been tied in the chipset since 80386 is out, afaik). The PIC will then decide what is the most important IRQ at any time and send an interrupt vector to the CPU (this is, the number of the INT to be executed).
The IRQ-to-INT vector mapping depends on how you (or ...) programmed the PIC. Default mapping is IRQ0-7 -> INT8-F and IRQ8-F -> INT 70-78, but this is unpractical for protected mode, so most (virtually all) of us remap IRQ0-F -> INT20-2F

3. What is an interrupt gate, and does it some way relate to I/O ports?

An interrupt gate is a descriptor that you'll put in the IDT to tell the CPU where (code segment and offset) it should go to handle a given interrupt. They are in no way related to IO ports.

4. I've found some code examples that look like this:
...

What I would like to know, however, is WHY these addresses, what is on address 10 or 6f for instance?
Is there possibly some good reference on this somewhere on the web?

The mapping of physical device to IO ports will not be found in the Intel manual, as it is independent from the CPU itself. I suggest you search the Web for a tool called 'HELPPC' which has the (almost) complete mapping of common IO ports for 80386 - compatible PCs.

And, fyi, IO port 10 is something related to DMA and 0x6F is unused.

I'd love some help

<voice char="Yoda">Help you want to have ? Help i will give to you</voice>

Pype.Clicker wrote:

4. I've found some code examples that look like this:
...

What I would like to know, however, is WHY these addresses, what is on address 10 or 6f for instance?
Is there possibly some good reference on this somewhere on the web?

The mapping of physical device to IO ports will not be found in the Intel manual, as it is independent from the CPU itself. I suggest you search the Web for a tool called 'HELPPC' which has the (almost) complete mapping of common IO ports for 80386 - compatible PCs.

You could also look for Ralf Brown's interrupt list (search yahoo or google for "RBIL Ralf Brown Interrupt List") and use PORTS.* from those files. They contain a very complete list of all the ports there are including a lot of additional stuff.

Small note though, since the advent of PnP, some ports can be remapped, altered and dynamically allocated, so there is, and will never be, a list of those ports. You have to use different methods to get to those devices. No worry though, these devices are all in the distant future for you.