Off topic:
2. 'linear address' is the address generated by the segmentation unit for the paging unit. This is typically a protected-mode concept, which absolutely do not fit the real-mode context you provided in your example.
Can't say I agree. IMHO linear = physical in real mode in exactly the same fashion as if paging is disabled in protected. The linear concept is just as valid in real mode as in protected mode because it gives a better sense of how memory is arranged than using the term physical.
On topic:
Think I understand the question (If I don't someone else might find this handy so I'll post anyway
):
The memory in a computer is usually addressed linearly. So if you have 1mb of memory then it is arranged as a list of bytes numbered sequentially from 0->0xFFFFF and if you read the byte at address 0x0 you are reading the value of the first byte in the list. I know this sounds obvious, but in other modes of addressing (Eg With paging) it is no longer true so I thought I'd make it clear.
While in real mode an Intel processor can only use registers that are 16-bits in size to address memory. The maximum address you can produce with 16-bits is 0xFFFF (64k). Since only being able to address 64k of memory is unacceptable the Intel designers came up with a solution that involves combining two registers to produce a larger address.
The solution is that an address in real mode has two components. A segment, and an offset.
An address is formed by multiplying the segment by 16 and adding the offset to it.
For example:
The real mode address:
0x7c00:0x0020
Is translated to a linear address using:
(0x7c00 * 16) + 0x0020
So the linear address the cpu will use to address the memory is:
0x7c020
(It's handy to work in hex because mutliplying the segment by 16 just involves putting a 0 on the end)
In essence the Intel designers have split up memory into 64k chunks (Segments). A side effect of this scheme is that you can create the same memory address in different ways (Eg 0x0FF0:0x00F0 = 0x0FFF:0x0000 = 0xFFF0 [linear]) another is that you can create a few addresses above 1mb.
Intel processors have a number of segment registers available to use.
CS - Code segment (This cannot be changed directly)
DS - Data segment
SS - Stack segment
ES - Extra segment
FS, GS - Rarely used in real mode.
Any instructions that address memory must have a segment and offset associated with it (Even if it isn't always obvious what they are). For example the 'lodsb' instruction reads the byte at DS:SI into al. As another example the 'push' instruction pushes a byte/word into memory at SS:SP and alters SP by the relevant amount.
There are also instruction which allow the programmer to specify the segment and offset registers to use (For example mov byte [GS:BP], 0x0). This action is referred to as a segment override because ordinarily DS would automatically be used as the segment.
In all cases of memory addressing it is the responsibility of the programmer to make sure the segment and offset are correct.
Ok, back on topic. In your example the segment register DS is put into ax, then multiplied by 16 (In eax because the result may be more than 16-bits long). This gives the base linear address of the segment. All offsets into the segment will be added to this base address to produce the final linear address. I think it's possible that this code is being used to store the base address of the data segment to make it easier to address variables once the switch to protected mode has been made.
In protected mode a different addressing scheme is used.
Hope that helps.