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Before I ask my question, I want to say hello to everyone! I used to come around here ages ago.
I'm not to familiar with protected mode yet but I'm learning :-\
What's better? Software or hardware context switching? (i386). What's the easiest to program for?
Thanks.

Hi, Both are not that easy. You will most probably need to implement both of them -as far as I could learn from gurus-, both has its own advantages, ... But people are tending to implement software one first, I did hardware one first, for my personal reasons... I think it is a matter of taste. As both have their own beauties, its good to learn them both.

People have said that software context switching is faster, but I find this to be hard to believe. However, I can see how software context switching would probably be superior in the case of reenterable interrupt routines.

software switches can beat hardware ones when you remain in the same address space. The switch in itself isn't dramatically faster, but just switching to another stack allow you to keep the CR3 register untouched, which means that further memory references will not experience a flushed Translation Lookaside Buffer.

The 80386 Programmer's Reference Manual is somewhat unclear on that point:

http://webster.cs.ucr.edu/Page_TechDocs ... 05_02.html

The existence of the page-translation cache is invisible to applications programmers but not to systems programmers; operating-system programmers must flush the cache whenever the page tables are changed. The page-translation cache can be flushed by either of two methods:

By reloading CR3 with a MOV instruction; for example: MOV CR3, EAX
By performing a task switch to a TSS that has a different CR3 image than the current TSS . (Refer to Chapter 7 for more information on task switching.)

Where did you get the information that leads you to believe that a TLB flush must be done even when the PDBR of the new task matches the CR3 of the old?

it seems newer documentation are less optimistics than the 80386 documentation manual (this comes from P4 system programming p 3-37):

All of the (non-global) TLBs are automatically invalidated any time the CR3 register is loaded (...). The CR3 register can be loaded in either of two ways:

• Explicitly, using the MOV instruction, for example: MOV CR3, EAX where the EAX register contains an appropriate page-directory base address.
• Implicitly by executing a task switch, which automatically changes the contents of the CR3 register.

The INVLPG instruction is provided to invalidate a specific page-table entry in the TLB.

According to my interpretation, any task switch will reload CR3, and thus flush the TLB content.

Implicitly by executing a task switch, which automatically changes the contents of the CR3 register.

Even that is unclear!

i don't see how it could be clearer! When you do a task switch, you implicitly reload the CR3 register, which results in a flush ...

Implicitly by executing a task switch, which automatically changes the contents of the CR3 register.

I can see how this would be unclear -- it could be interpreted two different ways in my mind:

1. They could be saying that executing a task switch will implicitly reload CR3 and invalidate the TLBs, regardless of whether the new CR3 value is the same as the old one.

or

2. They could be saying that whenever you execute a task switch that does in fact CHANGE the contents of the CR3 register then the TLBs are invalidated.

so, which is it???

NO! *wham*

Thou shalt read a sentence before argueing!

1. The sentence, Pype is citing, implies the following: At any time, when you perform a task switch, you have to switch cr3 values, when you use hard ware task switching with tss - to which the intel manual refers.

2. Using software task switching by stack switching, you have the choice to decide whether to switch cr3 too or not. If you only switch between threads: no cr3 reloading and tlb flushing; if you switch between full processes: cr3 reloading and tlb flush.

It is plain and clear.

HOS wrote: 2. They could be saying that whenever you execute a task switch that does in fact CHANGE the contents of the CR3 register then the TLBs are invalidated.

this would make sense if there was no comma (",") in the sentence. As my french teacher like to repeat, beware the commas, and don't mix

The sergent says : "the General is an idiot!"

with

"The sergent, says the General, is an idiot!

Pype.Clicker: I still believe that both of the references that we have cited have been unclear. Page 10-23 of the same manual states:

The following operations invalidate all TLB entries except global entries. (A global entry is one
for which the G (global) flag is set in its corresponding page-directory or page-table entry. The
global flag was introduced into the IA-32 architecture in the P6 family processors, see Section
10.5., ?Cache Control?.)
? Writing to control register CR3.
? A task switch that changes control register CR3.

We're going to have to run some tests or find other references to resolve this.

One questions about software task switching.

Everyone is telling me that if there is only a switch to another thread of a task I don?t need to change the cr3 reg. But I have to, because I need the value of the esp reg of the new thread and the task struc isn?t in the mem of a task.

How do you have solved this problem?

the task/process structure is what the kernel sees from the process ... the kernel flips process structures thro and fro ready and blocked and so forth queues. the task/process structure belongs to the kernel. the task must not fiddle around with it. It doesn't care about it.

the task/process structure is the kernels tool to assign the ressource "cpu" to tasks which want it.

The kernel has it's own memory region. In this memory region is stored the vital process data that keeps the processes spinning round the cpu.

for further information read some multitasking tutorial at www.osdever.net or at www.distantvoices.org

stay safe

You have missunderstood me!

I use paging and so every task has its own page table. If I want now to change to another task/thread I need the thread struc and this struc stands somewhere in the mem, but I can?t access it, because this mem region isn?t mapped into the page table of the task/thread and so I have to change the page table!

I hope you now understand what my problem is!