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Hi Guys,

I am stuck on this and cannot go on without it, which is why I am being so persistent. I have tried many examples, but this just will not work.

I have worked out that this code crahses as soon as I write the PG bit in cr0, I get an error from bochs that says '3rd Exception without Resolution'.

I really cannot go on until I have this done, and I have been trying to solve it myself, but without any luck.

The page directory and tables are 4kb aligned because I start the directory at 0x400000 and the tables at 4kb intervals after this.

; ===================================================
; Page Directory Address = 0x400000
; Page Table 0 = 0x401000
; Page Table 1 = 0x402000

; Format Page Directory Area
   mov      ax, 0x10               ; Load the Data Segment
   mov      es, ax                  ; Load the Segment Descriptor into ES
   xor      edi, edi               ; Clear EDI
   mov      edi, 0x400000            ; Starting Offset = 4MB
   mov      eax, 0x00000002            ; Table Address = 0, Supervisor, Read/Write, Not Present
   mov      cx, 0x400               ; Store 1024 DWORDs (EAX)
   cld                           ; Force EDI to be Incremented
   rep      stosd                  ; Store the Data

; Setup the Page Directory
   mov      dword [0x400000], 0x401003   ; Store Table0 Address, Supervisor, Read/Write, Present
   mov      dword [0x400004], 0x402003   ; Store Table1 Address, Supervisor, Read/Write, Present

; Indentity Map (0MB - 8MB)
   xor      edi, edi               ; Clear EDI
   mov      edi, 0x401000            ; Table0 Absolute Address
   mov      eax, 0x00000003            ; Starting Base Address = 0, Supervisor, Read/Write, Present
   mov      cx, 0x800               ; Store 2048 DWORDs (EAX)
   cld                           ; Force EDI to be Incremented
Map08MB:
   stosd                        ; EAX -> ES:EDI
   add      eax, 0x1000               ; Next Page Base Address
   loop   Map08MB                  ; Do Next Store

; Install the Page Directory
   mov      eax, 0x400000
   mov      cr3, eax

; Turn Paging On
   mov      eax, cr0
   or      eax, 0x80000000
   mov      cr0, eax

; Jump into Paging
   jmp      0x08:Paging
Paging:

; should be using paging now!!!
; =====================================================

Thanks.

There's no point waiting...

The thing about OS development, and especially paging, is that it is hard, and a lot of the time you need to figure things out for yourself. That's what I, and most of the experts, did.

If somebody does reply with a solution to your problem then you can consider yourself lucky. Until then, you should not expect somebody else to come along and fix your code for you.

i've been sweeping your code 2 or 3 times and found nothing that could explain things go that wrong. A few tips:
- install exception handlers and IDT before entering paging (so that a single exception doesn't reboot the whole thing) and try to have these handler giving you as much informations as possible ...
- try to simplify your table-generation code, so that you're absolutely sure that the table that will be generated IS the table you want
- check it by memory inspection if you can.
- light a candle to St. Dijkstra to avoid deadlocks
- find out the CPU registers values at crashs, where is the problematic point, etc... Code inspection rarely solve a problem when things becomes larger ...

Hi,

Thanks for your respnses. Tim, I was not expecting people to fix my code, I have been trying it for three days and I will contine to try until it is done. All the code in my OS so far is my own work, I have asked for help and I have taken and used advice, and if I have I used code from another OS then I have fully understood it until I would have written it the same or if possible I have made it better.

I am thankful for the help that I have received, but I do not want my OS written by other people, but why not benefit from those that have already overcome some of the most common problems.....

This is after all the whole point of this forum.

Thanks again.

Hi again,

I am not sure if I understand indentity mapping (linear = physical), Is my code above identity mapped?

as far as i've understood it should. However, what troubles me is that you declare all your page writable (bit 1 of the entry)...
But according to Intel docs, that bit is for giving writing access to DPL3 (user) code, and is only relevant when bit 2 (user mode readable) is also set. so, imho, setting bit 1 is not correct (though i do not think it could be harmful

What would happen if my kernel attempts to write to a page that does not have this (writable) bit set? Can DPL0 write to any page it wants?

i!f the page is present, it can -- unless you activate a special option in CR4 on pentium II+ that prevents kernel from writing read-only user pages (so that you can do copy-on-write for kernel too)

Actually, the WP bit is in CR0, and it applies to the 486 and above. It's bit 16 (mask = 0x00010000).

Not only is the WP bit essential for COW in kernel mode, it also helps trap writes to bad pointers that point somewhere into kernel code.

Hi,

Could someone pppplllleeeeaaaasssseeee... help me out, I cannot see the problem with the code above, when this code is taken everything goes perfect, my GDT and IDT are setup correctly and tested, so I know there must be a problem with this code, surely there is someone that has enough knowledge of Paging to work this out, even if you can just tell me that you have found a problem, at least I will know that there is one, and I can search for it, or you could be really nice and just tell what the problem is. This is the last thing that is done, my IDT is setup before this. I know that as soon as I set the PG bit in cr0 it crashes, because if I comment that line out it runs as normal, so I am guessing that there must be something wrong with the addresses or something like that.

If you need to know more specific stuff then let me know and I will post it. Also, I modified the code above because I made it smaller and slightly faster, but it does exactly the same as before.

Thanks.

Ok, I now know that the problem must be in the IRQ's because if I mask all IRQ's then everything runs fine. Only thing is that I thought IRQ's had nothing to do with Paging? Has anyone else encounter this? or do you think that there might be a problem in my IDT?

Thanks

Hi again,

To be more specific, the IRQ's that are causing the problems are, IRQ1 (System Timer) and IRQ2 (Keyboard) all other int's and IRQ's are working so far, any ideas?