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Hi~~~

I'm trying to write a kernel, and some of the memory need to be uncacheable.

I read the Intel document for PAT, and understand the following:

1.There is "IA32_PAT MSR" register holding 8 slot like the following: 2. Each of the lower 3 bit hold a figure that can represent the following caching type: 3. By manipulating PAT,PWD,PCD bit on each paging tables, I can select the slot I would like to use and decide the caching type.

4. For any structure including CR3 pointing to a page structure (paging table), it only use PWD,PCD to select caching type. In which only the first 4 entries in "IA32_PAT MSR" can be selected. Furthermore, it only effect the caching of the page structure it pointed to (such as CR3 point to a PML4E table, it only determine the caching type of the PML4E table)

5. For any structure that pointing to a physical page, it use PAT, PWD, PCD to select all 8 entries in "IA32_PAT MSR"
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So I would like to ask:

1. If the previews understanding are OK

2. Do I need to enable it, or it is automatically enabled if supported.

Thanks a lot!

shore wrote:some of the memory need to be uncacheable.

Why?

shore wrote:1. If the previews understanding are OK

Yes, but don't forget about MTRRs. The PAT and MTRRs both control how memory is cached.

shore wrote:2. Do I need to enable it, or it is automatically enabled if supported.

This is explained in the manual:

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A Section 11.12.1 wrote:Note that there is no separate flag or control bit in any of the control registers that enables the PAT. The PAT is always enabled on all processors that support it, and the table lookup always occurs whenever paging is enabled, in all paging modes.

Thanks a lot!

Just some of the MMIO memories need to be uncacheable....

The firmware has probably already configured the MTRRs to mark MMIO areas as uncacheable. Check the MTRRs.