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 Post subject: How to invalidate TLB on ARMv8?
PostPosted: Sat Jan 04, 2020 7:24 am 
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How do I invalidate TLB on ARMv8 CPU? This architecture has waaaaay too many different instructions for that purpose. The most suitable for whole TLB seems to be
Code:
TLBI ALLE1
but it is not available in EL1. And
Code:
TLBI VAE1, X0
for single page seems to do absolutely nothing (old mapping is still used).

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 Post subject: Re: How to invalidate TLB on ARMv8?
PostPosted: Sun Jan 05, 2020 11:44 am 
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Hi,

To invalidate the entire mapping on EL1 (same as reloading CR3 on x86), use
Code:
TLBI VMALLE1
DSB ISH
ISB
The first instruction invalidates the MMU. The second reloads the data cache, and the third the instruction cache.

To invalidate one page only (INVPLG on x86), do
Code:
DSB ISHST
TLBI VAAE1, (addr>>12)
The barrier is needed to flush pending cache operations. Note that TLBI does not expect an address, but a page number!

But on some ARM implementations with multiple cores and dcache, you'll need this:
Code:
DSB ISHST
TLBI VAAE1, (addr>>12)
DC CVAU, (addr)
DSB ISH
Not entirely sure why, but this is how the ARM Trusted Firmware does it. I'd recommend to check it out, it's on github, and it does lots of interesting things that are not documented at all. For example, when it sets the paging address in TTBRx_ELx, it also sets the lowest bit to 1 (and comment calls this CnP saying it is required for shared pages), which I have never read about in no docs nor specs, yet there it is...

Cheers,
bzt


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 Post subject: Re: How to invalidate TLB on ARMv8?
PostPosted: Sun Jan 05, 2020 1:19 pm 
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Thanks, man!
Adding that 12 bit shift worked like a charm. I would never suspect that it's needed there. I thought that addresses passed to TLBI instruction are just plain VAs.
TLBI VMALLE1 seems to work as well, yet its name and description in ARM docs are confusing. VM implies that some kind of virtualization is used.
But… it works!
Thanks again.

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