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Sorry, i am poor in english. understand my eng.
i try to switch task. but there is a problem with hardware task-switch.
the follow code is a log in bochrs when task switch occurs.
properly, i set up the map between tss and tss desc.
but when excute the instructon 'jmp far' ,my borchs had rebooting.
of course, Target task desc set up busy flag to zero ( type = 0x89 )

I designed like following step.

. map between tss struct and tss desc
. Main Task desc => 0x18 ( ltr 0x18 )
. Target Task desc to switch => 0x20
. set up busy flag to zero.
. JMP FWORD PTR addr ( addr = 0x20 )

* Actual code (vc++ eviroment)

  tmp = (word)&tss[0];
  setup_GDT_entry (&g_IdtTable[3], tmp, sizeof(TSS), 0x80|0x09, 0);
  
  tmp = (word)&tss[1];
  setup_GDT_entry (&g_IdtTable[4], tmp, sizeof(TSS), 0x80|0x09, 0);
  
  tss[0].trace = tss[1].trace = 0;
  tss[0].io_map_addr = tss[1].io_map_addr = sizeof(TSS);    
  tss[0].ldtr = tss[1].ldtr = 0x08;                
  tss[1].fs = tss[1].gs = 0;                    
  tss[1].ds = tss[1].es = tss[1].ss = 0x10;      
  tss[1].esp = (word)&task_stack+1024;    
  tss[1].cs = 0x08;
  tss[1].eip = (word)&Task_1;                    
  tss[1].eflags = 0x202L;                      

  __asm {
  push eax
  mov ax,0x18
  ltr ax
  pop eax
  }

  addr[0] = 0;
  addr[1] = (DWORD)0x20;  
  _asm JMP FWORD PTR addr



00004268727e[HD   ] device set to 0 which does not exist
00004269020e[HD   ] device set to 1 which does not exist
00004493485i[CPU  ] task_switch: bad LDT selector TI=1
00004493485i[CPU  ] task switch: posting exception 10 after commit point
00004493485i[CPU  ] -----------------------------------
00004493485i[CPU  ] selector->index*8 + 7 = 65367
00004493485i[CPU  ] gdtr.limit = 79
00004493485i[CPU  ] fetch_raw_descriptor: GDT: index > limit
00004493485i[CPU  ] | EAX=f000ff53  EBX=f000ff53  ECX=f000ff53  EDX=f000ff53
00004493485i[CPU  ] | ESP=0001ffdf  EBP=f000ff53  ESI=c00000e6  EDI=f000f84d
00004493485i[CPU  ] | IOPL=2 OV UP DI NG NZ NA PE CY
00004493485i[CPU  ] | SEG selector     base    limit G D
00004493485i[CPU  ] | SEG sltr(index|ti|rpl)     base    limit G D
00004493485i[CPU  ] |  DS:f859( 1f0b| 0|  1) 00000000 000fffff 1 1
00004493485i[CPU  ] |  ES:f841( 1f08| 0|  1) 00000000 000fffff 1 1
00004493485i[CPU  ] |  FS:e82e( 1d05| 1|  2) 00000000 000fffff 1 1
00004493485i[CPU  ] |  GS:efd2( 1dfa| 0|  2) 00000000 000fffff 1 1
00004493485i[CPU  ] |  SS:e739( 1ce7| 0|  1) 00000000 000fffff 1 1
00004493485i[CPU  ] |  CS:e3fe( 1c7f| 1|  2) 00000000 000fffff 1 1
00004493485i[CPU  ] | EIP=f000fea5 (f000fea5)
00004493485i[CPU  ] | CR0=0x60000019 CR1=0x00000000 CR2=0x00000000
00004493485i[CPU  ] | CR3=0x00000000 CR4=0x00000000
00004493485i[CPU  ] -----------------------------------