​[RFC] Freestanding C11 execution environment & MPU isolation for Cortex-M33

[EvaReinar12345]

Hello everyone,

​I am designing a strict, zero-allocation C11 freestanding execution environment targeting ARM Cortex-M33 (ARMv8-M) combined with post-quantum LWE/NTT cryptographic workloads.

​Core Architectural Pillars:

​Freestanding C11: -ffreestanding, -nostdlib, no heavy runtime dependencies, deterministic memory layout. ​Memory Isolation: Strict MPU region enforcement, page-locked execution arenas, and zero-allocation SPSC message passing. ​Cryptographic Bounds: Constant-time polynomial arithmetic and NTT for lattice-based structures.

​Looking for feedback or collaboration:

I'm interested in discussing optimal MPU boundary alignment techniques for low-latency interrupt handling on Cortex-M33 without incurring context-switch overhead.

​Technical contract and implementation blueprints are being structured. Thoughts or insights on handling strict hardware-enforced memory isolation for freestanding runtimes are very welcome.