quadrant wrote:
The sections in the region align nicely with 4096 byte pages - which I'm sure is no coincidence.
It certainly isn't. Most memory chips have a size that is an exact power of two in size. Other sizes you usually only get by adding multiple chips. This is simply because that way, if you have an address bus, the size of the chip is set by the size of the address bus of the chip, and you always have a valid address on it (example, if you have a 1024 byte ROM, it has ten address lines). Also, system bus design becomes a whole lot simpler if you naturally align your memory chips (so your 1024 byte ROM goes on a 1024 byte boundary), because that means the low address lines are just passed through to the ROM, and the high address lines can be used to decide which chip is selected. Nobody needs to do arithmetic on the addresses (like adding or subtracting offsets).
So most memory chips, and most register files, and most peripherals in general will have a size that is a power of two, and will be aligned to a power of two, and the only constraint needed to play well with 4k-paging is that the exponent be at least 12, which isn't hard for a video card, which needs tons of memory. At work I have three monitors in Full-HD resolution running with separate frame buffers. Try to calculate the memory requirements of that alone, never mind any back buffers the OS might have.
For ease of design, most system buses in the past were designed to use the high address lines to determine the chips to be selected. So unless they take more than the top twenty lines in a 32-bit system, everything will be nicely aligned for 4k-paging. And they won't because such large decoders would be expensive.