bzt wrote:
zaval wrote:
Yes, you are. You have confused "physical" addresses with "virtual" ones. His address is the latter, your quotes are about the former.
Is that so?
The quote is about the
relation between PA and VA on the ARM. ...
On ARM the virtual address size (called "output address size" in the quote) is not fixed, it must be configured.
Physical address bus width ("input address size" in this context) is not and cannot be software configurable, simply because that's hardwired into the chip. And that quote makes it perfectly clear that you cannot program VA size larger than the actual PA size.
Btw, have you ever tried to implement paging on RPi3?
Cheers,
bzt
dude, seriously, RTFM. Output address is PA. Always. It's from the MMU pesrpective - input is VA, output is (I)PA. And the quote you showed doesn't touch VA at all:
Quote:
If {I}PS is programmed to a value larger than the implemented PA size, then the PE behaves as if programmed with the implemented PA size, but software must not rely on this behavior. That is, the output address size is never larger than the implemented PA size.
PS field is "Physical address size". Or "intermediate physical address size" if HV is involved. "Output address" is physical address. It has nothing to do with VA space paramteres. Basically, it's about correct relation between writable TCR.(I)PS and hardwired ID_AA64MMFR0_EL1.PARange. Both of them describe physical addresses spaces only (as their names suggest).
Quote:
For each enabled stage of address translation, TCR.{I}PS must be programmed to maximum output address size for
that stage of translation, using the encodings as shown in Table D4-5.
"Each stage" here doesn't mean multi-level Page Tables, it means that it's either 1 stage VA->PA translation (a normal scenario) or 2 stage VA->IPA->PA (braindead HV scenario). For page tables it's termed "levels", and here - "stages". In both cases of this organization, (I)PS means "physical" address space size, "output address" means "physical" address.
VA space could be up to 512TB even if your system space is limited to only 4GB, with MMIO incl. as with the current Rockchip chips for example. It's up to the OS designer how much of "virtual memory" to support. The way you misunderstood, a so called "higher half" of VA spaces, is not possible at all on systems with the system space size less than or equal to 4GB, - thus on almost all SoCs found in modern SBCs. But it's not true! You just keep confusing things.
And of course, the kernel is loaded into the VA space, and the topic starter said that in the first line of his original post.
Quote:
Hi all, I have a generic question. After I enabling mmu on arm (aarch64), supposedly, kernel will be run at the high end of the virtual memory space (starts from 0xffff0000'00000000 in my mmu)...
You really confused things. Instead of arguing, try to clear it up by reading.