I've been trying, still can't get it. I might just try and use PAE or 4-level paging, but I highly doubt that one of those will work if this doesn't.
My current code is as such:
Code:
lea eax, [page_table - VIRT_BASE]
mov ebx, PT_PRESENT
mov ecx, (ro_end - VIRT_BASE)
shr ecx, 12
.fill_ro:
mov dword [eax], ebx ;insert entry
add eax, 4 ;next entry
add ebx, PAGE_SIZE ;next mem address
loop .fill_ro
or ebx, PT_READWRITE
mov ecx, (rw_end - VIRT_BASE)
sub ecx, (ro_end - VIRT_BASE)
shr ecx, 12
.fill_rw:
mov dword [eax], ebx
add eax, 4
add ebx, PAGE_SIZE
loop .fill_rw
;done with page table
lea ebx, [page_table - VIRT_BASE] ;load page table
or ebx, PD_PRESENT | PD_READWRITE ;set flags
lea eax, [page_dir - VIRT_BASE] ;load page dir
mov dword [eax], ebx ;move page table to 0 in page dir
add eax, PD_INDEX ;move to higher half entry
mov dword [eax], ebx ;move page table to higher half entry
lea eax, [page_dir - VIRT_BASE]
mov cr3, eax
mov eax, cr4
or eax, 0x00000010 ;enable PSE (4MiB pages)
mov cr4, eax
mov eax, cr0
or eax, 0x80010001 ;enable paging, WP, PE
mov cr0, eax
lea eax, [higher_half_start]
jmp eax
Not much different from before, just small changes.
The only thing
specific that I can think of is if I need to set PTE.PWT, PTE.PCD, or PTE.PAT, but I'm not sure, and I also doubt it. I've been looking through others' code, but can't seem to find any that are higher half, 32-bit, and separate RO and RW data. Could someone at least point me to that if they happen to know of a kernel that fits those requirements?