Hi,
JasonBond wrote:
I read about Process-Context Identifiers (PCIDs) for TLB/paging structure caches in Intel's manual but don't understand exactly how it should be used. For one thing, are there any real life OS (windows 10?) that is actually using it?
I don't know if any OS (Windows, OS X, Linux, *BSD, ..) supports it yet. It would be a relatively difficult thing to retro-fit into an existing kernel design (without breaking corner-cases, etc).
JasonBond wrote:
I suppose it is to prevent flushing some TLBs when we switch to a new CR3 and re-use the same TLB entries when switching back to a previous CR3 value. But the processor operation outlined in the intel's manual does not seem to support this. Exactly how does it benefit the performance?
Imagine the same CPU is rapidly switching between 5 different processes. In this case the performance benefit should be obvious - instead of blowing away all of a process' TLB entries every time you switch between processes, you don't (and should get a huge decrease in the number of TLB misses caused by task switching).
The problem is multi-CPU TLB invalidation, which can get expensive even without PCID (the more CPUs you have the worse it gets, in an exponential way). With PCID you can't assume that a CPU that is no longer running a process still doesn't have a TLB entry for that process; so PCID (if implemented in a simple/bad way) can make multi-CPU TLB invalidation overhead significantly worse.
To avoid making multi-CPU TLB invalidation overhead significantly worse you need something clever/complex; and it's this "clever/complex" that would make it hard to retro-fit into existing kernels that were never designed for it.
JasonBond wrote:
Are there anything similar in AMD?
That depends what you mean by "similar". AMD's virtualisation has had "Address Space IDs" for a long time, but they can only be used for guests running inside VMs.
Cheers,
Brendan