OSDev.org

The Place to Start for Operating System Developers
It is currently Fri Apr 19, 2024 7:53 pm

View unanswered posts | View active topics


Board index » Operating System Development » OS Development

All times are UTC - 6 hours




Post new topic Reply to topic  Page 1 of 1
  [ 11 posts ] 
  Print view Previous topic | Next topic 
Author Message
prinzrainer
 Post subject: I-32e Paging problem
PostPosted: Fri Jan 28, 2011 8:36 pm 
Offline
User avatar

Joined: Sun Nov 22, 2009 11:36 pm
Posts: 13
Just after setting the PG bit, there was a strange behavior.
Bochs' sayd something like this: "No linear - physical translation for addresss"
I've tried using "info tab" in bochsdbg. I was surprised that pages are mapped differently from
what I've expected. See below.

I am using BOCHS-2.4.1

Mappings info:
Address-Value
0x100000 - (quad) 0x0000000000101003 ; PML4->(PDPT @ 0x101000),P,R/W
0x101000 - (quad) 0x0000000000000138 ; PDPTE->(1GiB Page @ 0G),P,R/W,PS,G
0x101008 - (quad) 0x0000000040000138 ; PDPTE->(1GiB Page @ 1G),P,R/W,PS,G
0x101010 - (quad) 0x0000000080000138 ; PDPTE->(1GiB Page @ 2G),P,R/W,PS,G
0x101018 - (quad) 0x00000000C0000138 ; PDPTE->(1GiB Page @ 3G),P,R/W,PS,G

Cpu:
CR0 - 0xe0000011 ; PG,CD,NW,ET,PE
CR2 - 0;
CR3 - 0x00100000 ; PML4 @ 0x100(000)
CR4 - 0x000000a0 ; PGE,PAE
EFER - 0x00000500 ; LMA,LME

I have no idea of what the problem is.
Top
 Profile  
 
Tosi
 Post subject: Re: I-32e Paging problem
PostPosted: Sat Jan 29, 2011 8:41 am 
Offline
Member
Member

Joined: Tue Jun 15, 2010 9:27 am
Posts: 255
Location: Flyover State, United States
Most likely a problem in your page allocator.

_________________
Getting_Started on the wiki
x86 technical information
Interrupt Jump Table
Real Programmers Don't Use Pascal
My open-source projects

Top
 Profile  
 
Combuster
 Post subject: Re: I-32e Paging problem
PostPosted: Sun Jan 30, 2011 5:19 am 
Offline
Member
Member
User avatar

Joined: Wed Oct 18, 2006 3:45 am
Posts: 9301
Location: On the balcony, where I can actually keep 1½m distance
Not sure what you are trying to demonstrate with your custom dump, but the numerical dump says all of the address space is marked non-present while the other half of your dump says they are. (same concern holds for the writable and user bits)

Also, why is PSE off, and have you checked your emulated processor supports 1G pages?

_________________
"Certainly avoid yourself. He is a newbie and might not realize it. You'll hate his code deeply a few years down the road." - Sortie
[ My OS ] [ VDisk/SFS ]

Top
 Profile  
 
prinzrainer
 Post subject: Re: I-32e Paging problem
PostPosted: Sun Jan 30, 2011 7:58 pm 
Offline
User avatar

Joined: Sun Nov 22, 2009 11:36 pm
Posts: 13
Quote:
Not sure what you are trying to demonstrate with your custom dump, but the numerical dump says all of the address space is marked non-present while the other half of your dump says they are. (same concern holds for the writable and user bits)


oh, its:
0x101000 - (quad) 0x0000000000000183 ; PDPTE->(1GiB Page @ 0G),P,R/W,PS,G
0x101008 - (quad) 0x0000000040000183 ; PDPTE->(1GiB Page @ 1G),P,R/W,PS,G
0x101010 - (quad) 0x0000000080000183 ; PDPTE->(1GiB Page @ 2G),P,R/W,PS,G
0x101018 - (quad) 0x00000000C0000183 ; PDPTE->(1GiB Page @ 3G),P,R/W,PS,G

instead of 138...sorry..

I found out that bochs doesn't support 1GiB pages...so I turned to 2MiB pages and it works fine.
It seems that the PSE bit on cr4 determines only the for 4MiB PSE capabilities for 32-bit paging, doesn't it?
So how do I know really know if the processor support 2MiB PSE capabilities?
Top
 Profile  
 
a5498828
 Post subject: Re: I-32e Paging problem
PostPosted: Sun Jan 30, 2011 8:35 pm 
Offline
Member
Member

Joined: Thu Aug 12, 2010 7:25 am
Posts: 99
pse bit in control register is only for 32 bit paging. in pae its ignored, PS bit in paigng table is never ignored.
read the manual please, its all there.
Top
 Profile  
 
prinzrainer
 Post subject: Re: I-32e Paging problem
PostPosted: Sun Jan 30, 2011 10:47 pm 
Offline
User avatar

Joined: Sun Nov 22, 2009 11:36 pm
Posts: 13
Quote:
pse bit in control register is only for 32 bit paging. in pae its ignored, PS bit in paigng table is never ignored.
read the manual please, its all there.


That's what I'm telling you. Intel doesn't seem to tell how to identify support of 2MiB pages (in I-32e).. Since PS bit on cr4 is only for 32bit paging...


Last edited by prinzrainer on Mon Jan 31, 2011 2:01 am, edited 1 time in total.

Top
 Profile  
 
Hangin10
 Post subject: Re: I-32e Paging problem
PostPosted: Sun Jan 30, 2011 11:10 pm 
Offline
Member
Member

Joined: Wed Feb 27, 2008 12:40 am
Posts: 162
*edit: not relevant*


Last edited by Hangin10 on Mon Jan 31, 2011 2:07 am, edited 1 time in total.

Top
 Profile  
 
prinzrainer
 Post subject: Re: I-32e Paging problem
PostPosted: Mon Jan 31, 2011 2:02 am 
Offline
User avatar

Joined: Sun Nov 22, 2009 11:36 pm
Posts: 13
I meant 2MiB pages....
Top
 Profile  
 
Combuster
 Post subject: Re: I-32e Paging problem
PostPosted: Mon Jan 31, 2011 3:07 am 
Offline
Member
Member
User avatar

Joined: Wed Oct 18, 2006 3:45 am
Posts: 9301
Location: On the balcony, where I can actually keep 1½m distance
The relevant part of the manual:
AMD 2-5.3.2 wrote:
The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging.

_________________
"Certainly avoid yourself. He is a newbie and might not realize it. You'll hate his code deeply a few years down the road." - Sortie
[ My OS ] [ VDisk/SFS ]

Top
 Profile  
 
prinzrainer
 Post subject: Re: I-32e Paging problem
PostPosted: Mon Jan 31, 2011 3:20 am 
Offline
User avatar

Joined: Sun Nov 22, 2009 11:36 pm
Posts: 13
Combuster wrote:
The relevant part of the manual:
AMD 2-5.3.2 wrote:
The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAE automatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging.


So in I-32e, 2MiB pages is always supported?
Top
 Profile  
 
gravaera
 Post subject: Re: I-32e Paging problem
PostPosted: Mon Jan 31, 2011 3:47 am 
Offline
Member
Member
User avatar

Joined: Tue Jun 02, 2009 4:35 pm
Posts: 737
Location: Supporting the cause: Use \tabs to indent code. NOT \x20 spaces.
Did you read the manual to see?

_________________
17:56 < sortie> Paging is called paging because you need to draw it on pages in your notebook to succeed at it.

Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  Page 1 of 1
  [ 11 posts ] 

Board index » Operating System Development » OS Development

All times are UTC - 6 hours


Who is online

Users browsing this forum: Google [Bot], MichaelPetch and 171 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB © 2000, 2002, 2005, 2007 phpBB Group