AndrewAPrice wrote:
I was reading through the
Microsoft documentation on memory management and it mentions Inverted Page Tables. Is it practical to implement IPT on x86?
How do you tell the CPU that this virtual address maps to this physical address? The documentation I read online goes into talking about the hashing and lookup mechanisms, but nothing about how to implement it on x86.
You'd still need the processor's paging structures, but there would be only one set? I'm imagining that in long mode, you'd have a single PML4 that'd get cleared on context switches, so every memory address would cause a page fault, and you'd rebuild the paging structures each time slice?
As pointed out by others, hardware inverted page tables are a feature of the hardware architecture. It's not something x86 can implement.
A big benefit being able to bound the size of the table regardless of the virtual space used.
A big problem is that because the table is indexed by physical page number, you can't directly map a VPN to a PPN, and instead have to hash the VPN and walk PPN entries that match the hash, so hardware walking is a bit more involved than, but like the multiple access required for a hierarchical page table (as used on x86), this extra latency is hidden by the TLB.
A good comparison of various processors can be found here:
https://drum.lib.umd.edu/handle/1903/7465This is originally an IEEE publication from 1998, so predates amd64, for example, but also include Alpha MMU.
It also includes PA-RISC's (IMO whacky) 96-bit VA MMU.