alexfru wrote:
It's not a memory address in ICW2. It's the base interrupt number (bits 7 through 3 of it; bits 2 though 0 are zeroes). By default the interrupt numbers are 0x08+0...7 (for master PIC/IRQ0...7) and 0x70+0...7 (for slave PIC/IRQ8...15).
Ooooh, thank you so much!
Would it be useful to change the addresses from the default? I think I read somewhere that the 0x08+0...7 addresses are reserved by the CPU or something, would it perhaps be a good idea to change the interrupt numbers for the master PIC to 0x80+0...7?
And just to make sure I'm absolutely certain here - say my PICs are configured to their default address settings, and IRQ0 interrupts, the CPU would then look up the 0x08th entry in the IDT?
Thanks!
EDIT: I just worked out the answer to my first question there, yes the first 32 interrupts are reserved to be interrupts for exceptions