| OSDev.org https://forum.osdev.org/ |
|
| Is there any MMIO without read/write side effect? https://forum.osdev.org/viewtopic.php?f=15&t=31905 |
Page 1 of 1 |
| Author: | jcyangzh [ Fri May 12, 2017 9:11 am ] |
| Post subject: | Is there any MMIO without read/write side effect? |
Quote: The simplest system memory model does not use memory-mapped I/O with read or write side effects, does not include a frame buffer, and uses the write-back memory type for all memory quote from Intel® 64 and IA-32 Architectures Software Developer’s Manual I wondering is there any MMIO without read/write side effect. For example, assume there is a keyboard device which is memory-mapped to system memory. Suppose the address of data is data_addr, the address of command is cmd_addr. To read from the keyboard, cpu issue read(data_addr) => data_addr mapped to the keyboard reigster which contains the scan code of the previous keyboard press => cpu cache the memory of data_addr. The cpu could not get the next keyboard press until the cache of data_addr is invalidated, because the next read from data_addr hits the cache. The same procedure applies to the write process. So is there any MMIO without read/write side effect? What is read/write side effect? |
|
| Author: | Korona [ Fri May 12, 2017 9:57 am ] |
| Post subject: | Re: Is there any MMIO without read/write side effect? |
This simple system memory model the SDM (?) is talking about does not include MMIO. A read/write side-effect is an action (other than reading/writing the memory location targeted by the read/write) that is taken because of the read/write. Many (but not all!) registers have write side-effects, e.g. an ATA controller might move a HDD's head in response to a write, and start reading data. Some registers even have read side-effects: For example there are devices that have "did-interrupt-fire" registers that unasserted the interrupt once they are read. An example for memory that has neither read nor write side-effects video memory that is used for a framebuffer or a texture. In your example no cache would be involved because MMIO with read/write side effects will be mapped as uncachable in the MTRRs. |
|
| Page 1 of 1 | All times are UTC - 6 hours |
| Powered by phpBB © 2000, 2002, 2005, 2007 phpBB Group http://www.phpbb.com/ |
|