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 Post subject: Question about the paging
PostPosted: Mon Apr 23, 2018 8:10 am 
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Joined: Sat Aug 27, 2011 9:25 am
Posts: 6
Question about the paging.
I map first (64+8)GB memory 1:1
Whether it is possible to mix 1GB pages and 4KB pages?
How to map video memory from 0xA0000-0xAFFFF at 0x1101000000 (68G+16M)?
Code:
MaxMemV =       64+8                    ;72GB

        mov     ebx,512*8*(1+1)

        push    ebx

        mov     ebx,1024*1024           ;CR3=1M
        mov     [PML4],ebx
        lea     eax,[ebx+4096]
        mov     [PDP],eax

        pxor    mm0,mm0
        pop     ecx
        shr     ecx,3
      @@:
        dec     ecx
        movq    [fs:ebx+ecx*8],mm0
        jnz     @B

        mov     eax,[PML4]
        mov     ebx,[PDP]
        mov     edx,ebx
        or      bl,7
        mov     [fs:eax+8*000],ebx

        mov     eax,1024*1024*1024
        movd    mm1,eax
        mov     eax,1187h
        movd    mm0,eax
       ;Fill page tables
        xor     ecx,ecx
      .1:
        movq    [fs:edx+8*ecx],mm0
        paddq   mm0,mm1
        inc     ecx
        cmp     ecx,MaxMemV
        jb      .1


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 Post subject: Re: Question about the paging
PostPosted: Mon Apr 23, 2018 8:52 am 
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Joined: Sat Mar 31, 2012 3:07 am
Posts: 4161
Location: Chichester, UK
Yes, you can map 4K pages and 1G pages in the same page table (in IA-32e mode). But note that not all processors that support IA-32e mode support 1GB pages, so you really need to check first (and make alternative provision if necessary). Unless you are careful, 1GB page mapping can be wasteful of resources. I prefer to keep it simple and use just 4K pages; this is, IMO, a far more flexible option.

You map a region of video memory in exactly the same way that you would map any other area of memory.


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 Post subject: Re: Question about the paging
PostPosted: Mon Apr 23, 2018 10:21 am 
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Joined: Sat Aug 27, 2011 9:25 am
Posts: 6
can you present mixing sample code?


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 Post subject: Re: Question about the paging
PostPosted: Mon Apr 23, 2018 11:11 am 
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Joined: Sat Mar 31, 2012 3:07 am
Posts: 4161
Location: Chichester, UK
No.

It's all clearly explained in the Intel manuals.


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