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collected a few infos about Ultra DMA https://forum.osdev.org/viewtopic.php?f=1&t=8339 |
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Author: | Pype.Clicker [ Sun Jun 08, 2003 7:38 am ] |
Post subject: | collected a few infos about Ultra DMA |
Hi dudez. I just thought it could interrest some of you. I'm actually doing researchs on how Ultra DMA (fast access to IDE disks without the intervention of the CPU for transferring bytes from the disk to the memory or vice-versa :p ) works and how it can be enabled. Here's are my results so far:
Hope it helps More info to come when i'll be done. Oh, btw, so far, i have the feeling that BOCHS doesn't support UDMA operations, so it will be for my |<r@$|-| machine to test |
Author: | Pype.Clicker [ Mon Jun 09, 2003 3:43 am ] |
Post subject: | Re:collected a few infos about Ultra DMA |
hmmm ... from reverse-engineering of linux "ide-dma.c", it appears that the 'descriptor table' is made of 2x32bits entries. The first dword in each entry is the dma address of the chunk and the second dword is actually used on 16bits only and is the size (highest bit of the size is the termination bit). Note that chunks may not cross a 64Kb barrier (as far as i know) and may not be larger than 64KB either. A 0x0000 size is usually representing a full 64KB size, but some controllers misinterprete this as a 0 size, so linux split all 64K chunks in 2 32K chunks on the fly. -- update -- intel Chipset datasheet confirms the Physical Region Descriptor Format. I have trouble finding out how one actually access the PCI configuration space. i know I/O ports 0xCF0..0xCFF are involved, but i don't know neither how nor which one exactly ... What is usually presented as memory-mapping configuration space looks like not being mapped at all ??... Tim or anybody else that has worked on PCI already, if you have some docs reference ... -- update -- this article seems to hold good info about how to access the PCI configuration space. |
Author: | Pype.Clicker [ Wed Jun 25, 2003 5:55 am ] |
Post subject: | Re:collected a few infos about Ultra DMA |
okay. so obviously, access to PCI configuration space is made by writing the configuration address (made of bus, device, function numbers plus offset for that function -- see above proposed PDF link) to port 0xCF8 and then reading/writing the data from port 0xCFC (watch out sideeffects like security holes in ozone layer :p ) |
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