burzin wrote:
Yes I do set up the PCI command register, that is very confusing. The ICH8 data sheet
says UHCI is hardwired to disable MMIO, I enable port io and bus mastering. Then
how does the controller access the frame list and buffers, but it works anyhow.
MMIO is mapping device registers into the memory address space. UHCI registers are defined in terms of IO port space, not memory mapped space (as indicated by PCI BAR0 bit 0).
The frame list is referenced by the
Frame List Base Address register. That points to memory in the PCI device address space, which is access using PCI busmaster DMA. On PCs, that address space often corresponds to the same physical address space used by RAM memory, but it may not be so if the PCI device address space is mapped using an IOMMU.
The frame list itself points to queue heads (QH) and/or transfer descriptors (TD), which are the data structures which actually point to buffers, and again, those buffers are accessed using PCI busmaster DMA in the PCI device address space.