Bonfra wrote:
Well actually one more thing before I proceed on fixing my bogus MSD implementation...
UHCI specs page 20 wrote:
Frame Lists are aligned on 4-Kbyte boundaries. Transfer Descriptors and Queue Heads must be aligned on 16-byte
boundaries
In fact,
on line 207 I allocate TDs with alignas(0x10) and it works great.
Later, on the same function, where I
allocate the queue head at line 238 if the queue head is just aligned to 0x10 it doesn't work, it gets stuck (on real hw). If instead it's aligned to 0x1000 it works fine. Is there any specific reason for this or is it just some random quirk that I should respect?
"Allocate" seems a bit optimistic. You allocate it on the stack as an automatic variable.
I'm assuming you have 1:1 linear->physical page mapping as well, as you appear to be using the linear stack address as is.
You write this QH address straight to the frame list schedule, in each frame. So you're using a shotgun approach to ensure your QH is executed.
But, when your function is done, it makes no attempt to reset the frame list schedule to remove the presumably now processed QH, instead it is left on the schedule, and the UHCI controller will continue to examine it.
If you put it on the stack, what will be happening is that your stack location for the QH will be overwritten with other function values, which is probably messing up your controller as it'll be reading garbage from the QH.
I'd recommend:
1. Allocating both the QH and TD using non-automatic stack based storage.
2. Once your QH is processed, remove it from the schedule.
3. Design a better schedule, that points to static queue heads, onto which you can attach your temporary QH. If you have Ben's USB book (which I highly recommend), it will have the details of how to lay out the schedule.