Barry wrote:
passerby wrote:
It didn't fault when switching PML4, it faulted when CPU executed these lines of code: (in kernel/arch/x86_64/mmu.c)
Step it in a debugger, find out which instruction is causing the fault. It may be an issue quite deep down the call stack in your PMM. If you've got a page-fault handler that can tell you about the error, it's worth checking the saved RIP value and taking a look at the instructions at and around that location; this is probably easier to do than stepping, but only if you have the handler working.
passerby wrote:
And can I know how does Limine map higher half kernel?
Parse the paging structures it uses, you can find them the same way the CPU does.
Thanks for your advice, but can I ask a question? When I was reading the Limine PROTOCOL.md, I found a request tag called Higher Half Direct Map, what is that mean? I'm confusing, the RIP points to 0xffffffff80000000, and HHDM tag's offset field contains 0xffff800000000000, can you explain this for me?