I didn't read your question properly, sorry for that (my fault for trying to answer a question in a haste).
I assume you're using MSI or MSI-X. In that case the IP is cleared automatically.
Intel xHCI manual, page 291 wrote:
If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled, then the
assertion of the Interrupt Pending (IP) flag in Figure 4-22 generates a PCI Dword
write. The IP flag is automatically cleared by the completion of the PCI write.
So, from my understanding, how the IP flag works is:
- If IMODC == 0, then IP = 1
- If IP == 1, then generate interrupt and clear it immediately
So when you receive the first interrupt, the bit gets cleared.
When the second interrupt is generated (i.e. IP is set to 1) it stays at 1 because it can't generate an interrupt due to EHB not being cleared.
Also, this is why I think it's important to emphasize the -er in interrupter, as it is something that generates an interrupt. It is not something that represents an (active) interrupt.