nullplan wrote:
That is a good idea. Changing from x86 to x86_64 is a change of architecture, and that can be difficult as you start out. So if you start at x86_64, you have less changeover pain.
That is good to know.
nullplan wrote:
The AMD64 GDT is basically the same structure as the i386 one. The only differences are that the system call instructions prescribe a certain order of segments, and that you need two segments wherever you actually specify a nonzero base address (the upper segment containing only the high 32-bits of the base address). But I've only ever needed that for the TSS. The TSS looks different in 64-bit mode, and yes, you still need one if you ever plan to switch to user mode. Consult the Intel SDM vol. 3A or AMD APM vol. 2 for more information (depending on taste, really, they basically contain the same information).
So if I understood correctly, I don't need to learn something new (which usually takes me from a couple of months to a year or two).
nullplan wrote:
You enable paging on AMD64 the same way you do on i386. In fact, you have no choice but to enable paging, since the instruction that enables paging is the instruction that switches to long mode. The page table format is the same as the PAE format (please consult the SDM or APM for details). Only now the third layer is actually a full layer, not just four entries, and there is a fourth layer of page tables. Otherwise, it is pretty similar, just a nice, hierarchical page table system. Switching CR3 requires the page that the instruction is on to be on the same physical page before and after the switch, so that requirement hasn't changed. Most OSes achieve that by mapping the kernel the same way in all address spaces.
I don't think I need to do this since I'm using BOOTBOOT, which automatically loads the kernel into higher half and supports x86_64 kernels. I'm not sure how BOOTBOOT sets up paging though (if it even does).
nullplan wrote:
As for AArch64, GDT and IDT are entirely x86-specific concepts and simply don't exist on any other architectures. They are an outgrowth of the 8086's interrupt handling mechanism and the 80286's overloading of the segment registers, respectively, and no other architecture has these chips in its lineage. I am unfamiliar with AArch64 specifically, but I do know ARM8 had its interrupt table at a fixed address in memory (no idea if that was virtual or physical memory, and there were ARM8 chips that didn't have paging at all, making the distinction moot). I do know that most RISC CPUs have only a single exception for "external interrupt", and if you want to know more specifically what interrupt occurred, you need to ask the interrupt controller. In any case, I suggest you get some documentation on AArch64 interrupt handling if the topic interests you. But I would counsel against putting two architectures on your plate from the start. Get your OS going on one arch, then the other.
Will do. Thanks.