xeyes wrote:
1. Wiki's ATA article says "On some drives it is necessary to "manually" flush the hardware write cache after every write command.", is this still the case for SATA drives?
As far as I'm aware, it's not necessary for any drives. You do need to flush the write cache before turning the power off, though. I suspect the author of that statement forgot this step. (The flush may be performed as part of setting the drive to a low-power mode. You'll have to look at the various ATA and ACS specifications for details.)
xeyes wrote:
2. What are the differences between DMA and PIO cmds? Doesn't data always move inside data FISes on the sata bus and are DMAed to/from system memory by the HBA? There might be minor differences like PIO vs. DMA setup FISes but are there good reasons to use one vs. the other?
PIO has worse error handling and may not be able to transfer more than one sector per command. The AHCI specification explains it in more detail, but in short you should always prefer DMA over PIO.
xeyes wrote:
3. What should the direction (command header DW0 bit 6) be for cmds that don't move data between the device and system memory such as 0xE7? Is there a spec with these details?
According to the AHCI spec, it should only be set for writes, so use 0 for commands that are not writes.
xeyes wrote:
4. Are the bits in port command issue (PxCI) register ORed together with the value written by the CPU? Or can the CPU clear bits there as well by writing 0?
According to the AHCI spec, writing a 1 sets the associated bit and writing a 0 does nothing. The AHCI spec additionally mentions that you should only set PxCI bits you want to change - do not write a 1 to a bit that is already set.
xeyes wrote:
5. I assume that the HBA doesn't detect data hazard among different cmds in different slots and the software is supposed to keep track of that?
Correct.
xeyes wrote:
If that's true, how should software enforce the ordering?
That depends on the commands you're using.
xeyes wrote:
If the software always sets 1 bit at a time in CI (in quick succession without waiting for the the set bits to clear), would the order of completion be the same and the cmd whose bit is set earlier always completes earlier?
According to the AHCI spec, commands are typically posted in the order they're issued, and most commands complete in the order they're issued. The exceptions are port multipliers, which may cause commands to be issued in a different order, and NCQ commands, which may complete in a different order. Read the AHCI spec for details.
xeyes wrote:
What if the software sets multiple bits in CI with a single one write? Does the HBA have any preference or the commands could complete in any order?
According to the AHCI spec, if you issue multiple commands with a single write, they may be posted in any order.
I notice a lot of your questions are answered by the AHCI specification...