laen wrote:
Is it defined once for a standard device class (let's say all AHCI devices share the same bus mastering configuration mechanism for PCI bus mastering) or is it defined for one particular PCI device (let's says seagate SSD) or something in-between?
Standard devices implement bus mastering according to the specification. For example, the AHCI specification says all AHCI controllers must implement bus mastering in the same way, so you only need to write one driver to support all AHCI controllers. On the other hand, PCI IDE controllers are not required to implement bus mastering, so a vendor could choose to add some vendor-specific bus mastering hardware instead of following the standard.
In theory, a vendor could add vendor-specific bus mastering hardware alongside the standard bus mastering hardware, but I doubt it's very common.
laen wrote:
This I understand, I was trying to say in the memory hole meant for this purpose, which is marked as "reserved" for the bios int 0x15, eax=0xE820. I guess calling it RAM is wrong as RAM refers to physical memory.
The firmware memory map doesn't include available addresses. PCI MMIO can't use reserved addresses, typically because some other device is already mapped there. Keep in mind the firmware memory map is not complete: it doesn't include PCI or ACPI devices.
laen wrote:
So, if I get your point, the aim is to tell the PCI device "rather than me writing and reading to your memory which is slow (through addresses in the MMIO pointed by BARs) and take up a lot of CPU time, read periodically the info I write in this memory space in physical memory and answer in this other physical RAM space, and when you are done answering tell me by toggling this interrupt through MSI". Did I get this right?
Usually you still need to access MMIO to notify the device when you've written info into memory; otherwise that's correct.