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Bizarre RTC behaviour in QEMU
https://forum.osdev.org/viewtopic.php?f=1&t=56010		 Page 1 of 1
Author:  HJVT [ Wed Dec 01, 2021 6:26 am ]
Post subject:  Bizarre RTC behaviour in QEMU
Reading register A always yields 00100000, IRQ8 despite being enabled and unmasked never fires, and reading time yields values like 84:65.

What could be going wrong?

P.S. I'm very new to osdev, so please ELI5.
Author:  waltster [ Wed Dec 01, 2021 4:17 pm ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
Hi,

What is the context of this situation? What bootloader are you using? When you say "register A", what was the proceeding context to the read? Providing these kinds of notes helps us to understand where issues are coming from and how we can help!

Best,
W.
Author:  Octocontrabass [ Wed Dec 01, 2021 7:45 pm ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
HJVT wrote:
Reading register A always yields 00100000

What are you expecting to see?

HJVT wrote:
IRQ8 despite being enabled and unmasked never fires

When the lowest four bits of register A are set to 0b0000, the RTC periodic IRQ is disabled. You need to write a different value to those bits to enable the IRQ.

HJVT wrote:
and reading time yields values like 84:65

You need to interpret the values differently according to register B. For example, if register B says BCD 12-hour time, then 0x84 in the hours register means 4 PM.
Author:  HJVT [ Thu Dec 02, 2021 3:29 am ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
Octocontrabass wrote:
What are you expecting to see?

I am expecting the update bit to change. Although I am only reading time on PIT interrupts.

Octocontrabass wrote:
When the lowest four bits of register A are set to 0b0000, the RTC periodic IRQ is disabled. You need to write a different value to those bits to enable the IRQ.

I am initialising the RTC in the way the wiki describes:
Code:
port0x70.write(0x8Au8);
port0x71.write(0x20u8);

port0x70.write(0x8Bu8);
let prev = port0x71.read();

port0x70.write(0x8Bu8);
port0x71.write(prev | 0x40);

This seems in fact to clear lower bits of register A. I'm unsure why the wiki claims that this will result in periodic interrupt being enabled?

Octocontrabass wrote:
You need to interpret the values differently according to register B. For example, if register B says BCD 12-hour time, then 0x84 in the hours register means 4 PM.

That could explain what I'm seeing, but I am not reading hours, only minutes and seconds:
Code:
port0x70.write(0x8Au8);
let update: u8 = port0x71.read();
if (update & (1 << 6)) == 0 {
    let time = unsafe {
        port0x70.write(0x80);
        let sec = port0x71.read();

        port0x70.write(0x82);
        let min = port0x71.read();
        format!("{:02}:{:02}", min, sec)
    };
}
Author:  Octocontrabass [ Thu Dec 02, 2021 8:56 am ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
HJVT wrote:
I am expecting the update bit to change. Although I am only reading time on PIT interrupts.

That's probably not often enough to catch it, but it doesn't help that you're doing it in a VM. Actual hardware usually has separate clock sources for the RTC and the PIT, but on a VM the two might use the same clock source and therefore never drift relative to each other.

HJVT wrote:
I'm unsure why the wiki claims that this will result in periodic interrupt being enabled?

There's no one proofreading the wiki, so it doesn't do a very good job of explaining that setting register A is not part of the initialization sequence. (Although maybe it should be - is there any guarantee the firmware will always set register A to 0x26?)

HJVT wrote:
That could explain what I'm seeing, but I am not reading hours, only minutes and seconds:

It's BCD. 84 is 0x54 and 65 is 0x41, so the time is 54:41.
Author:  HJVT [ Thu Dec 02, 2021 10:41 am ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
Octocontrabass wrote:
There's no one proofreading the wiki, so it doesn't do a very good job of explaining that setting register A is not part of the initialization sequence. (Although maybe it should be - is there any guarantee the firmware will always set register A to 0x26?)

I see. With setting A to 0x26 I now receive an interrupt, a single one, despite reading register C on interrupt which is supposed to signal to RTC that interrupt has been handled and it is okay to send another one:
Quote:
It is important to know that upon a IRQ 8, Status Register C will contain a bitmask telling which interrupt happened. The RTC is capable of producing a periodic interrupt (what this article describes), an update ended interrupt, and an alarm interrupt. If you are only using the RTC as a simple timer this is not important. What is important is that if register C is not read after an IRQ 8, then the interrupt will not happen again.

However, the wiki only mentions register C as related to time on the RTC page, the CMOS page doesn't mention this register at all, despite listing out other time-related registers.

Edit: Reading external links on CMOS page at least clarifies the meaning of register C bits.
Author:  Octocontrabass [ Thu Dec 02, 2021 12:50 pm ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
HJVT wrote:
I see. With setting A to 0x26 I now receive an interrupt, a single one, despite reading register C on interrupt which is supposed to signal to RTC that interrupt has been handled and it is okay to send another one:

Did you also acknowledge the interrupt in the interrupt controller(s)?
Author:  HJVT [ Fri Dec 03, 2021 6:13 am ]
Post subject:  Re: Bizarre RTC behaviour in QEMU
Octocontrabass wrote:
Did you also acknowledge the interrupt in the interrupt controller(s)?


Oh, totally forgot that.
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