Octocontrabass wrote:
Ethin wrote:
Hell, I don't get why I'd need its IDT. I've got my own.
Do you? The IDTR in the logs you've posted looks an awful lot like it's pointing to the OVMF IDT instead of yours.
Yes. I think so. I load my gDT and IDT before my VMM is initialized. I've tried moving it up quite far in the initialization chain. And it still triple faults (I haven't yet allocated a kernel heap). The registers look like this (from the qemu monitor):
Quote:
RAX=0000008000001fd8 RBX=000000007ff156b8 RCX=0000000000359f08 RDX=0000000000000000
RSI=000000800000e068 RDI=0000008000001fd8 RBP=000000007fb7e014 RSP=0000007fffffbee0
R8 =0000000000000004 R9 =000000000000000a R10=000000800000e0c0 R11=0000000000000059
R12=000000014000f070 R13=000000007ff155e8 R14=000000007ff15320 R15=000000007ff150c8
RIP=000000000024f817 RFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 0000000000000000 ffffffff 00cf9300
CS =0008 0000000000000000 ffffffff 00af9b00
SS =0010 0000000000000000 ffffffff 00cf9300
DS =0010 0000000000000000 ffffffff 00cf9300
FS =0030 0000000000000000 ffffffff 00cf9300
GS =0030 0000000000000000 ffffffff 00cf9300
LDT=0000 0000000000000000 0000ffff 00008200
TR =0010 00000000002fe8b8 00000067 00008900
GDT= 00000000002fe930 0000001f
IDT= 00000000002fe9c0 00000fff
CR0=80010032 CR2=000000000000bede CR3=0000000000002000 CR4=00000668
DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
DR6=00000000ffff0ff0 DR7=0000000000000400
EFER=0000000000000d00
FCW=037f FSW=0000 [ST=0] FTW=00 MXCSR=00001f80
FPR0=0000000000000000 0000 FPR1=0000000000000000 0000
FPR2=0000000000000000 0000 FPR3=0000000000000000 0000
FPR4=0000000000000000 0000 FPR5=0000000000000000 0000
FPR6=0000000000000000 0000 FPR7=0000000000000000 0000
XMM00=00000000000000000000000000000000 XMM01=00000000000000000000000000000000
XMM02=00000000000000000000000000000000 XMM03=00000000000000000000000000000000
XMM04=00000000000000000000000000000000 XMM05=00000000000000000000000000000000
XMM06=00000000000000000000000000000000 XMM07=00000000000000000000000000000000
XMM08=00000000000000000000000000000000 XMM09=00000000000000000000000000000000
XMM10=00000000000000000000000000000000 XMM11=00000000000000000000000000000000
XMM12=00000000000000000000000000000000 XMM13=00000000000000000000000000000000
XMM14=00000000000000000000000000000000 XMM15=00000000000000000000000000000000
My kernel shows:
Quote:
[INFO] [kernel] Loading descriptor tables and enabling interrupts
[INFO] [libk::gdt] Loading GDT
[DEBUG] [libk::gdt] Loading GDT at addr 0x2fe930: GlobalDescriptorTable { table: [0, 49428545226735615, 150838860841063, 0, 0, 0, 0, 0], next_free: 4 }
[INFO] [libk::gdt] Setting CS
[DEBUG] [libk::gdt] CS at addr 0x2fe978: SegmentSelector { index: 1, rpl: Ring0 }
[INFO] [libk::gdt] Loading TSS
[DEBUG] [libk::gdt] TSS at addr 0x2fe8b0, TSS selector at 0x2fe97a: TSS = Lazy { cell: Once { data: TaskStateSegment { reserved_1: 0, privilege_stack_table: [VirtAddr(0x0), VirtAddr(0x0), VirtAddr(0x0)], reserved_2: 0, interrupt_stack_table: [VirtAddr(0x301ea0), VirtAddr(0x311ea0), VirtAddr(0x359ea0), VirtAddr(0x0), VirtAddr(0x0), VirtAddr(0x0), VirtAddr(0x0)], reserved_3: 0, reserved_4: 0, iomap_base: 0 }}, init: ".." }, TSS selector = SegmentSelector { index: 2, rpl: Ring0 }
[DEBUG] [libk::gdt] TSS at addr 0x2fe8b0 with TSS selecter at addr 0x2fe97a loaded
[DEBUG] [libk::gdt] Changed TR; old: 0, RPL_0 | TI_GDT, new: 10, 0x10
[INFO] [libk::interrupts] Loading IDT
[DEBUG] [libk::interrupts] IDT loaded. IDT at 0x2fe9c0: [snipped - IDT is huge]
[DEBUG] [libk::interrupts] Changed IDT: old: 7F274018 with limit FFF, new: 2FE9C0 with limit FFF
I don't use an STI/CLI instruction -- I'd assume that interrupts are (already) enabled... Does UEFI disable those after exiting boot services?