Octocontrabass wrote:
What happens if you also set bit 5 when you clear bit 4?
One source suggests that it might be necessary.
Good idea. I haven't tried that yet.
The current mode of operations is:
1) Read CRTI, keep a backup (so don't interfere with a program that is about to change a CRT register)
2) Reset bit 4. That should acknowledge the interrupt, but keep it disabled (as I read the manual)
3) Clear bit 5, allow the interrupt.
4) Set bit 4, allow the interrupt to trigger again.
5) Restore CRTI.
Probably I should keep bit 5 set until the very end (in step 4).
On a cirrus GD542x, the sequence is quite simple ("from the book"), replace 2) to 4) by just "clear bit 4", "set bit 4", and you are good, but the S3 seems to be somewhat "special" (again).
Now that I read the procedure: Is it true that on the PC IRQ 2 is edge-triggered or level-triggered? The way how the S3 manual reads is that the output of the IRQ flip-flop is directly connected to the interrupt controller such that setting the bit to 1 manually is indeed required to receive another HI-LO flank.
It is level-triggered on this particular system, meaning that setting the bit to HI could indeed trigger the interrupt again?
Octocontrabass wrote:
If there really is no way to stop it from constantly triggering an interrupt during vertical blank, then the best solution would be to disable the interrupt (set bit 5) in the handler and use a timer or something to re-enable it after vertical blank has ended.
Well.... if I had a timer. This is a bit touchy as this is a driver that should not interfere with other system resources.