Octocontrabass wrote:
The ROM needs it, since the ROM runs in real mode, but you don't need it. You can tell the ROM to set up a mode that uses a linear frame buffer. Of course this assumes the hardware supports a linear frame buffer; the datasheet implies that you can't have a linear frame buffer in planar modes.
Well, I'm not quite sure where the manual states that. I can (by means of GR6) get a 128K "linear"/planar frame buffer, but that is as far as it gets. As soon as I enable the "linear" mode by means of LAWControl/CR58, plane addressing is gone and I am more or less back to a plane-interleaved "mode X" like frame buffer.
The Cirrus chips have an additional bit that extends the VGA memory to 256K by disabling the adress wrap-around. There is a similar register for the VirGE (CR31 bit
, except that clearing it gives only 128K, whereas setting it gives you only a 64K window. SR4 bit 1 (ext mem) is of course set.
Octocontrabass wrote:
Section 12.7 of the datasheet is pretty clear on how you enable the vertical blank interrupt, but you won't see anything happen until you configure your interrupt controller(s) appropriately. How are you configuring the interrupt controller?
Not clear enough, I afraid. It does not mention additional interrupt sources (LBP) you only find after reading the additional section about the MMIO registers, and it does not state how the MMIO interrupt handling interacts with the old-style I/O VGA interrupt handling, e.g. if the VSP bit is set in case of an MMIO interrupt as well and whether I need to clear the interrupt bits there as well.
The problem is not so much that I do not get interrupts - the problem is that when I get them, the corresponding I/O or MMIO registers do not indicate that there actually was an interrupt. Thus, I cannot clear the interrupt as the same interrupt line is also used by other sources in the system. In fact, the MISC and INPUTSTATUS1 bits are all bogus and read all zero, so I cannot even busy-wait for a vertical blank, and the same goes for the MMIO registers.
No, the chip does not sit behind a traditional PIC, it is not in a PC system here. It sits behind PAULA, but the problem is not at this end. Other interrupt sources on the same bus work, and even the Virge seems to trigger interrupts, just that I do not get a reliable status that they have been triggered. In fact, once VBlank has been triggered, the system is locked as the interrupt is coming back after the interrupt service routine as the interrupt status does not indicate a pending interrupt source at all.