sunnysideup wrote:
0. Can most of today's motherboards be "logically" considered as this?
The only logical view you can have on the motherboard is the one presented to the CPU. And it is this: The CPU is directly connected to some memory. Ask BIOS (Int 15h, Function E820) or UEFI for how much and where it is. It is also directly connected to some peripherals in address space. Ask ACPI and the PCI bus about where and what. Other than the ISA devices (which are all the legacy devices like PIT, PIC, ISA DMA controller, etc., and, of course, the PCI controller), you find all your hardware on the PCI bus like it was 1995. Only difference now is, if you can support it, you can talk to PCI config space using MMIO. Ask ACPI about details.
sunnysideup wrote:
1. The first issue that I see with this picture is that it isn't multiprocessing. If it were, how would the diagram vary?
Depends, but it is unlikely you would notice until you're getting quite deep into the architecture of things. And right now you don't even have USB drivers
. There were multi-socket main boards (and they still exist and are used for servers and stuff), in which multiple CPUs (multiple physical packages) would be slotted into different sockets, often each with their own memory attached. All CPUs could still see all memory, but accessing non-local memory would require requests to be routed across the MB and thus take longer (the North Bridges would handle that, no need for software support). It is therefore advantageous to allocate memory for a CPU in the memory closest to the CPU. Such an architecture is called NUMA. These days you usually have SMP systems, in which there is only one CPU package containing multiple cores, often multiple threads in those cores. But all memory is still accessed locally, so unless there is cache contention, all memory accesses take the same time. Such an architecture is called UMA.
For your picture not much changes, except you have a battery of CPUs (instead of a single one) attached to either one (UMA) or a battery (NUMA) of North Bridges. And from the point of view of the OS running on the CPUs, you see no difference since all hardware beyond the CPU is still the same. So long as not multiple CPUs try to talk to the same hardware, everything works out the same.
sunnysideup wrote:
2. I know that OLD (very very old PCs) used something called an ISA bus. Has it been replaced? Has it been removed? Is there a bus with similar functionality in today's motherboards?
The ISA bus is what the PC clone industry called the PC standard. It still exists. Your PCI bus will have an ISA gateway somewhere, and reading about ICHs and PCHs you might come across a thing called the LPC bus, which is just the ISA bus with fewer pins. Instead of running with 32 pins at 4MHz, they are running with 4 pins at 32MHz, but the throughput is the same. I'm oversimplifying here, obviously, but you were not making hardware for the thing, you were just looking to program it.
The PCI bus allows for a standard way for hardware to tell the OS and BIOS about the resources it needs, and otherwise, for functionality, it offers much of the same things as ISA. These things work with transactions now, but that also does not matter to the OS programmer. And the various iterations of PCI over the decades (i.e. AGP and PCIe) also don't matter to the OS programmer. Only the MMIO way of accessing the PCI config space is an innovation you might want to take on board, but is for a decently designed OS only a local optimization.
sunnysideup wrote:
3. Where would the IOAPIC and the LAPIC be located on this board?
The IOAPIC is inside the South Bridge (low speed device). The LAPIC is inside the CPU (in each thread, really).
sunnysideup wrote:
4. Is the ATA controller present in the disk drive or on the motherboard?
Motherboard. MB ATA controller talks to the Integrated Disk Electronics on the drive in a standard way, but that is one step removed from the CPU. The CPU only talks to the ATA controller, and then that thing works some black magic you neither know nor care about, and then your sector appears in memory somewhere.
sunnysideup wrote:
5. I've programmed the timer (that corresponds to port numbers 0x40 and 0x43). Where is this located?
Inside the South Bridge. As is most legacy hardware. Even the RTC.
sunnysideup wrote:
6. Is the PCI controller (busmaster?) located in the southbridge (ICH)?
What does it matter to you? You talk to a PCI device, say a RAID controller, then it does something, and then another hard disk sector appears in memory. You don't need to talk to the PCI device any more than that, and you don't need to setup the DMA transfer like you needed with ISA, so how exactly those bytes get from the disk into the memory is something you don't have to care about.
Picture this: Imagine I told you an answer, and it was wrong. How would you notice? You can't; the entire process does not concern you.
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