Hi,
To invalidate the entire mapping on EL1 (same as reloading CR3 on x86), use
Code:
TLBI VMALLE1
DSB ISH
ISB
The first instruction invalidates the MMU. The second reloads the data cache, and the third the instruction cache.
To invalidate one page only (INVPLG on x86), do
Code:
DSB ISHST
TLBI VAAE1, (addr>>12)
The barrier is needed to flush pending cache operations. Note that TLBI does not expect an address, but a page number!
But on some ARM implementations with multiple cores and dcache, you'll need this:
Code:
DSB ISHST
TLBI VAAE1, (addr>>12)
DC CVAU, (addr)
DSB ISH
Not entirely sure why, but this is how the
ARM Trusted Firmware does it. I'd recommend to check it out, it's on github, and it does lots of interesting things that are not documented at all. For example, when it sets the paging address in TTBRx_ELx, it
also sets the lowest bit to 1 (and comment calls this CnP saying it is required for shared pages), which I have never read about in no docs nor specs, yet there it is...
Cheers,
bzt