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| PCIe Link Speed Retraining https://forum.osdev.org/viewtopic.php?f=1&t=33945 |
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| Author: | johnsa [ Tue Aug 27, 2019 7:41 am ] |
| Post subject: | PCIe Link Speed Retraining |
Hi, After a long break from OS related tinkering I thought I'd give it another go, this time using UEFI which has actually been pretty pleasant. I'm doing some work on PCIe specifically, (for a specific device) .. so from the configuration space offset 0x34 I've followed the pointers to find the PCIe extended configuration structure (id = 0x10). From here I've used offset 0x04 to determine maximum payload (which I set through offset 0x08). In my case it's 256bytes. The link capabilities register gives a max link width of 0x16 and a max link speed of 3 (from register offset 0x0c). The link status register (0x12) is showing me negotiated link width of x16 (so nothing to do there) but a current link speed of 1. Using register 0x30 (Link Control 2 Register) I set bits 0:3 to link speed 3. Using register 0x10 (Link Control Register) I set bit 5 to trigger a link re-train. The I wait a small duration (1second just for debugging) In a polling loop I test bit 11 of the Link status Register (Link Training) until it's clear. Read the info back from link status register (0x12) and it's still showing me a link speed of 1. Do I need to configure the de-emphasis values as well ? Perhaps someone can shed some light on the correct process to correctly set and retrain the PCIe device link to a higher speed. Thanks! John |
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