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After enabling mmu on arm (aarch64)
https://forum.osdev.org/viewtopic.php?f=1&t=33354		 Page 2 of 2
Author:  zaval [ Tue Dec 11, 2018 9:09 am ]
Post subject:  Re: After enabling mmu on arm (aarch64)
bzt wrote:
zaval wrote:
You really confused things. Instead of arguing, try to clear it up by reading.

You should consider your own advice. Start with that 512G address space you keep repeating. JFYI, the architectural limit of ARMv8 is 52 bits as a starter. Second, write PoC and try that out. I'm afraid I cannot help you more. Some people are just beyond hope.

Good bye,
bzt

#facepalm. what 512GB address space? You better acknowledge that you finally got it you were wrong instead of playing the fool.
Of course, you cannot help if you still can't distinguish between pieces talking about PAs and talking about VAs and worse, - don't want to go and learn.
but last time, again, I told about the 512TB VA space limit. for especially gifted, I show the quote:
Quote:
In AArch64 state, the VA address space has a maximum address width of 48 bits. With a single VA
range this gives a maximum VA space of 256TB, with VA range of 0x0000_0000_0000_0000 to
0x0000_FFFF_FFFF_FFFF.
However, for the EL1&0 translation stage the VA range is split into two subranges, one at the
bottom of the full 64-bit address range of the PC, and one at the top, as follows:
• The bottom VA range runs up from address 0x0000_0000_0000_0000. With the maximum
address width of 48 bits this gives a VA range of 0x0000_0000_0000_0000 to
0x0000_FFFF_FFFF_FFFF.
• The top VA subrange runs up to address 0xFFFF_FFFF_FFFF_FFFF. With the maximum address
width of 48 bits this gives a VA range of 0xFFFF_0000_0000_0000 to 0xFFFF_FFFF_FFFF_FFFF.
Reducing the address width for this subrange increases the bottom address of the range.
This means that there are two VA subranges, each of up to 256TB.
Each translation regime, that takes a VA as an input address, can be configured to support fewer
than 48 bits of virtual address space,

This is from the architecture version, relevant to RPi3 Cortex-A53. And this one quote contains enough information for a willing one to get he was mistaken. But it's not about you.
You failed to acknowledge you messed it up. it speaks about you and you know, I don't care about your unwillingness to listen, you have proven your inability to discuss normally before, not to mention - take the fact you are mistaken. my intention was to point out to your mistakes, so that you won't confuse the topic starter with your wrong claims.
Author:  Schol-R-LEA [ Tue Dec 11, 2018 11:25 am ]
Post subject:  Re: After enabling mmu on arm (aarch64)
I suggest that you both calm down and step away from this thread for a bit. It's getting a bit heated, and for little reason.

Perhaps we can let the OP reply, giving them a chance to let us know the outcome from the initial advice? I have an interest in this question myself, so I'd like to hear what they have to say about whether they got it working or not, and how.
Author:  kzinti [ Wed Dec 12, 2018 6:15 pm ]
Post subject:  Re: After enabling mmu on arm (aarch64)
Why is there no moderator acting on this thread? This tone and insults in these messages have no place on this forum.

I would suggest locking the thread and giving both a warning.
Author:  thepowersgang [ Thu Dec 13, 2018 12:48 am ]
Post subject:  Re: After enabling mmu on arm (aarch64)
(MODERATOR NOTE)
I've split out the last two posts by zval and bzt (moved to a hidden forum), as they were getting a bit too heated.
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