BaconWraith wrote:
So just for final clarification, when it says "IRQ"
here in this article on the wiki, does it really index the 'global interrupt numbers'?
No. It means the specific IRQ line on that specific I/O APIC. Like Brendan explained the GSI system, if you have two I/O APICs, for example, the first with 20 IRQ lines, and the second with 10 IRQ lines. GSI 2 would correspond to IRQ 2 on the first I/O APIC, while GSI 20 would correspond to IRQ 0 on the
second I/O APIC, and GSI 26 would correspond to IRQ 6 on the second I/O APIC.
BaconWraith wrote:
QEMU has only the one IOAPIC, with 24 pins afaict, so do the ISA IRQs map to pins 0 through 15 on this IOAPIC?
Yes.
BaconWraith wrote:
Atm, I'm remapping the i8259 PICs to 0x20-0x2F and masking everything (why shouldn't I mask the cascade as well, does it prevent the spurious interrupts from being handled correctly?)
In theory, masking the cascade prevents
all slave PIC IRQs from happening, and the slave PIC IRQ is connected to the master, which is why you need to EOI the master in the slave's spurious IRQ handler. So personally, I don't think the cascade should be masked, although there probably aren't any real harms from doing it.
BaconWraith wrote:
Last question, you say you map all of the IOAPIC inputs to 0x30 onwards - if I only want to handle certain ISA interrupts can I just leave all the others masked in the APIC, or is it good practice to unmask and assign them all to a interrupt vector?
Just like the PIC, you leave all IRQs masked, and when you initialize a device driver that uses an IRQ, you unmask that device's IRQ line.