JamesHarris wrote:
Edge triggering makes sense for PIT timers but what happens when a PC's PIT timer fires an IRQ (IRQ 0) on a machine which has exclusively level-triggered interrupt recognition?
I've found an answer to this in the book The IBM PS/2 From the Inside Out. It turns out that when IBM went from ISA to MCA they added an extra latch. Crucially, a PIT ISR would need to reset the latch so a timer ISR on an MCA machine needs extra code.
For PS/2 designs IBM added an "IRQ-0 latch" between the PIT and the PIC. When the timer output is asserted (presumably by an edge, as before) the latch is triggered. Its output is then asserted and remains asserted, i.e. it provides the level assertion that the PIC needs.
It is up to the interrupt service routine to reset the latch. It does that by setting bit 7 of port 0x61 (system control port B). It look as though resetting the latch is necessary or the interrupt signal will not be removed from the PIC.
Incidentally, the book says that the latch is reset by setting SCPB bit 7 to one but I suspect from other references I've found that that bit would also need to be reset to zero so that the latch receives a reset pulse.