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 Post subject: RTC interrupts
PostPosted: Thu Apr 27, 2017 10:55 am 
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Posts: 40
Hi all

I've got the keyboard interrupt and Exception etc. interrupts working well but trying to get the RTC timer interrupt to work is proving difficult. I've programmed the offsets for the PIC and setup the interrupt for the timer (if it was incorrect it's prints a message i.e. a catchall message) and set the mask to enable the IRQ but cannot get it to do anything. After three days of trying it's time to ask! The code below is cobbled together from various sites (as you can see from the comments) along with my own code. The vector settings for the PIC are below (all code running in 64 bit long mode) :-

Code:
   %define PIC1      0x20      ;IO base address for master PIC */
   %define PIC2      0xA0      ; IO base address for slave PIC */
   %define PIC1_COMMAND   PIC1
   %define PIC1_DATA   (PIC1+1)
   %define PIC2_COMMAND   PIC2
   %define PIC2_DATA   (PIC2+1)
   %define PIC_EOI      0x20      ;End-of-interrupt command code */
   %define PIC_MO      0x20      ;Offset for master
   %define PIC_SO      0x28      ;Offset for slave
   %define ICW1_ICW4   0x01      ; ICW4 (not) needed */
   %define ICW1_SINGLE   0x02      ;Single (cascade) mode */   
   %define ICW1_INTERVAL4   0x04      ; Call address interval 4 (8) */
   %define ICW1_LEVEL   0x08      ; Level triggered (edge) mode */
   %define ICW1_INIT   0x10      ; Initialization - required! */

   %define ICW4_8086   0x01      ; 8086/88 (MCS-80/85) mode */
   %define ICW4_AUTO   0x02      ; Auto (normal) EOI */
   %define ICW4_BUF_SLAVE   0x08      ; Buffered mode/slave */
   %define ICW4_BUF_MASTER   0x0C      ; Buffered mode/master */
   %define ICW4_SFNM   0x10      ; Special fully nested (not) */

   in al,PIC1_DATA         ;Save mask for master
   mov r8b,al
   in al,PIC2_DATA         ;Save mask for slave
   mov r9b,al
   mov al,ICW1_INIT+ICW1_ICW4
   out PIC1_COMMAND,al         ;starts the initialization sequence (in cascade mode)
   out PIC2_COMMAND,al         ;
   mov al,0x20
   out PIC1_DATA,al            ;ICW2: Master PIC vector offset
   mov al,0x28
   out PIC2_DATA,al            ;ICW2: Slave PIC vector offset
   mov al,4
   out PIC1_DATA,al            ;ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100)
   mov al,2
   out PIC2_DATA,al            ;ICW3: tell Slave PIC its cascade identity (0000 0010)
   mov al,ICW4_8086
   out PIC1_DATA,al
   out PIC2_DATA,al
   mov al,r8b               ;Restore saved masks
   out PIC1_DATA ,al         ;
   mov al,r9b               ;
   out PIC2_DATA,al            ;


The Setting up of the RTC for timer interrupts is below :-

Code:
mov al,0x8b                  ;RTC Registers
   out 0x70,al                  ;select register B, and disable NMI
   in al,0x71                  ;read the current value of register B
   mov ah,al
   mov al,0x8b
   out 0x70,al                  ;set the index again (a read will reset the index to register D)
   or ah,0x40
   mov al,ah
   out 0x71,al                  ;write the previous value ORed with 0x40. This turns on bit 6 of register B
   mov al,0xd
   out 0x70,al
   
   in al,PIC1_DATA               ;Get mask register
   mov al,0xfd                     ;mask everything except keyboard for now
   out PIC1_DATA,al
   in al,PIC2_DATA               ;Get mask register
   mov al,0xfe                     ; mask all except RTC
   out PIC2_DATA,al


I must be missing something simple as it all looks OK to me with the only possible problem being that it is in a VM.

Bipman


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 Post subject: Re: RTC interrupts
PostPosted: Thu Apr 27, 2017 11:52 am 
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Joined: Thu Aug 06, 2015 6:41 am
Posts: 90
Location: Netherlands
Bipman wrote:
Code:
   in al,PIC1_DATA               ;Get mask register
   mov al,0xfd                     ;mask everything except keyboard for now
   out PIC1_DATA,al


I forgot about this the first time too, but you also need to unmask IRQ 2 because that's where the slave PIC is at.
From the wiki:
wiki.osdev.org wrote:
When a bit is set, the PIC ignores the request and continues normal operation. [...] Masking IRQ2 will cause the Slave PIC to stop raising IRQs.

Also reading a register and then completely overwriting it (instead of AND'ing or OR'ing) is pointless

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Lithik


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 Post subject: Re: RTC interrupts
PostPosted: Fri Apr 28, 2017 7:16 am 
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Joined: Wed Mar 15, 2017 9:22 am
Posts: 40
That did it thanks! I read that piece of text without thinking about how I'd have to enable it, keep getting the 1 for mask and the 0 for unmask mixed up. The reading and then writing was just laziness on my part as I didn't alter the code I used.

Bipman


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