Sergio wrote:
- I understand, from Intel SPG part 1 that local apic is enabled at boot. Is it still enabled after BIOS? or is the master 8259 connected directly to the INT/NMI pins? what about the ioapic? is it enabled? if so, is it acting as a 8259? is its outputs connected to LINTS? or directly to the processor interrupt pins INT/NMI? I really feel like needing a better background to this point to be able to understand how I might latter further configure an interrupt system.
The bios leaves you off in an environment that functions just like an old PC-AT, and it disables/changes the hardware settings to get there. That indeed means that the local apic is disabled and interrupts are generated from a virtual 8295 PIC.
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- Does the APIC system work in real-mode?
- What happens to the APIC/8259 when going to protected-mode?
Hardware can not see what happens inside the CPU execution unit. That means the interrupt wiring does not magically change between real and protected mode, and the processor will just get the same interrupts at the same time. One problem however is that the 16 bits of real mode are not enough to address the interrupt-related hardware and make the changes - you need at least 32-bit addresses for that. That does not mean you can go back to real mode and enjoy an APIC-based setup.
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- Is this mechanism (probing buses) unnecesary/unreliable?
Hardware detection is generally required, and you need something that tells you what's in the box. However for most buses there is a starting point that can give you a full list: the PCI bus will give you most peripheral devices, ACPI will get you most chipset specifics, which means you only really need to probe one thing. You may assume that the architecture-defined devices (like the PIT and KBC) just exist without needing to actually probe them. The only problems come from having an ISA bus, which is the only time you'll need to try every known device to see if they happen to be there.
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- According to the state of the APIC/8259 up to here, I mean, because I really ignore if the CPU is receiving interrupts directly from 8259 or through the local apic: if in legacy mode (8259 interrupts the CPU directly), can I still use the MP/ACPI table mechanism for devices? if receiving interrupts from local apic, are legacy devices connnected to ioapic? are they connected to 8259 and this, in turn, connected to ioapic?
Interrupts should "appear" to come from a 8295 in legacy mode. There are several variations on how this is arranged, and the tables should tell you how exactly. It does mean you should be prepared for all such configurations.
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- Probing devices the old way, how can I probe devices behind the PCI-ISA bridge?
Guess where they are, then try if they respond as expected.
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- The result of device probing tells me, through the INTERRUPT LINE from PCI configuration space registers what IRQ all devices are issuing, but then I see that the PCI-ISA bridge, which is a multifunction device part of the SB600 chip from amd, issued IRQ0. In fact all functions from this device have IRQ0 at the INTERRUPT LINE. Is this valid?
The INTA you see listed on the PCI configuration is not necessarily wired to IRQ0 (actually, you're in trouble if it is since the PIT doesn't like sharing interrupts), nor is it necessarily used. Also, the ISA bridge does not define how interrupts from devices behind it are routed - you just have an extra set of wires called IRQ0..15 that are going from somewhere to somewhere.