>On 2002-03-19 10:43:52, DarkEyes wrote:
> I truly hope that who ever this reaches can answer my question or can atleast point me to the answer. And thanks in advance
>
> Anyway my question is this does the AMD Athlon XP or lower handel protected mode in Assembly differently than an Intel x86(PIII in this case)?
I really doubt it, dude. Unfortunately, it's probably
a small problem with your code. Without a doubt,
they probably handle this stuff different _internally_,
but the programmer, it should be completely the
same.
> My problem is this. I have implemented into my Kernel for my OS Protected mode. What I have done for the time being is written a simple IDT/Handeler that re-routes all interrrupts to a Real Mode segment which in turn calls the true Bios interrupt and then returns to the Protected Mode Code. The code is simple(only 30lines) and works well on my Aptiva 550(Pentium III 500mhz), I have tested it throughly.
Impressive, dude! I think a lot of people would be
interested in that source code (myself included) if
you wouldn't mind posting it.
That's one area where I stumbled when making my OS.
I assume you're using vm86 mode for this? As far
as I know, this is the only possible way.
>Note that both the code segments and interrupts are given Ring0 preivlegives but I have tried all different combinations with no success.
>
>Here is how it Works on the Pentium III(Correctly):
>Protected Mode Interrupt(say int 13h)->IDT->Handel->Real Mode Segment of Code->Calls Corresponding Bios Interrupt(Calls the real int 13h)->Returns to PMode code that called.
>
>Here is how it works on my AMD Athlon4(Incorrectly):
>Protected Mode Interrrupt->Skips to the next line of code
It _skips_ the line!? That is seriously strange.
So the program doesn't crash or triple fault...
it runs... just not correctly?
The only thing I can suggest is that interrupts
are disabled, but you say they aren't? Hmmm...
what about nmi's?
> I littered my whole code with Debugging so I know that it is skipping only the interrrupts and going everywhere else. Also I Do have interrupts enable via Sti. I have made extensive checking and Sti doesn't seem to have an effect on the transfer to the interrupts. In the IDT I have tried both Interrupt Gates and Trap Gates.
Yeah, I doubt would do anything... it doesn't even
look like the processor is even checking the IDT!
I wonder... if you put values in the IDT that are
_blatantly_ wrong (say 0xfffff....), what happens?
Does it triple fault, or simply skip the line
still?
>Please help in anyway that you can. If I don't fix this one silly bug then I wont be able to continue. I have looked every where on the web for answers and usually no one knows or just gives false information. I had one guy tell me that cli enables interrupts and sti disables them :p, which I tried anyway just because I had nothing else :p.
CLear Interrupts enables them!? HAH
Where'd
you get that response from?
Out of curiousity, are you actually debugging
with a debugger, or just using the ol' "beep/print"
method to flag certain parts of the program
as they execute?
Is it possible that you might be misinterpreting
your debug code if using the latter?
>One last note on the Intel I seem to still be able to call software interrupts even with them disabled.... maybe this could point to one difference I have found.
Yeah, that's something I've never understood!
It's pretty stupid, if you ask me. And, when you
can actually mask off the "non maskable interrupts"...
weird!
>P.S Please Email me if you can in anyway help.
Unfortunately, I don't think I was too much help,
but perhaps if you can submit you code, someone
might be able to find the error. I'd also be
quite interested to see what you've done.
Jeff
PS: if the Athlon and PIII were that much different
that legacy OSs like OS/2 and Win95 wouldn't run
propely on them...
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