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 Post subject: Higher Half + 4 MiB Pages, Now Can't Access VGA
PostPosted: Sun May 15, 2022 11:47 am 
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Joined: Thu May 12, 2022 6:04 pm
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I recently implemented a higher half kernel with 4 MiB paging, borrowing from the various Bare Bones tutorials on this site. I am now running into an issue where I can't write to the VGA, whereas I could before with 4 KiB pages.

My understanding is that with PSE enabled, each page directory entry points to a 4 MiB page. This means that for the higher half kernel to work, I need to identity map the first 4 MiB of physical memory to the first 4 MiB of virtual memory (by writing 0x00000083 to the corresponding page directory entries 0 and 768).

Using GDB and QEMU, I can see that CR3 is populated with 0x104000, the physical address of my page directory. I can also see that the page directory has 0x00000083 set at entry 0 and 768 by the time I call kernel_main(). However, for some reason, while debugging with GDB I do not hit my breakpoint in kernel_main. I'm wondering if somehow I mapped the page directory wrong.

Additionally, I changed the address of VGA to 0xC00B8000. My understanding is that since 0xB800 lies within the first 4 MiB, this should be properly mapped to virtual memory.

You can find my code here: https://github.com/mttarry/osdev.

Files to note:

kernel/kernel.c
kernel/arch/i386/boot.S
kernel/arch/i386/tty.c
kernel/arch/i386/linker.ld

Thanks in advance!


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 Post subject: Re: Higher Half + 4 MiB Pages, Now Can't Access VGA
PostPosted: Sun May 15, 2022 7:27 pm 
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Joined: Mon Mar 25, 2013 7:01 pm
Posts: 3872
You forgot the $ on this instruction, which results in garbage in ECX, which causes an exception when trying to load that garbage into CR4.

There are other issues in this code too; this is just where it gets stuck when I debug it.


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