PCI IDE control bar I/O address?
Posted: Fri Aug 01, 2025 7:37 am
I just looked at the PCI IDE controller information (https://wiki.osdev.org/PCI_IDE_Controller and https://wiki.osdev.org/Talk:PCI_IDE_Controller).
Trying to emulate a i440fx PIC IDE controller, I now know two things, from experience with how the BIOS configures it:
- Although an user named Giawa (https://wiki.osdev.org/index.php?title= ... &redlink=1 ) says that the controller I/O base address is at +0, this can only be at +2, because the I/O BARs of the PCI specification don't allow using bits 0 and 1 (https://en.wikipedia.org/wiki/PCI_configuration_space , bit 0 must be 1 to designate an I/O BAR and bit 1 is reserved, so it requires a 32-bit base I/O port alignment by design).
- Seeing as how the i430fx for example configures the PCI IDE controller of it's own motherboard, if found configurable (according to it's official documentation, interestingly enough, BAR4 exists, but BAR 0/1/2/3 isn't documented at all, probably non-existent and forced to 0 (doubleword), which isn't documented either (some BARs might be unimplemented on real chipsets and forced to 0 when that is the case). i430fx seems to use them to move ATA controllers, where somehow the second ATA controller can be moved up to the primary controller's I/O address (and the secondary I/O ports unused), seen from setting up the BIOS setup in different ways). usually it's the defaults however (1f0,3f0,170,370 for BARs 0-3, BAR4 is dynamically assigned depending on the hardware however (The IDE DMA registers' I/O ports)).
Anyone knows what the actual behaviour is on real PCI IDE controllers (whether onboard or plugin cards)?
Edit: Also, how does the command register bits affect legacy and PCI IDE port addresses, if at all for legacy? Does it disable the legacy I/O ports too?
Edit: Also, the bottom two links (PCI IDE Controller Specification (http://www.bswd.com/pciide.pdf , which seems to be https://www.isdaman.com/alsos/hardware/hdc/pciide.pdf) and Programming Interface for Bus Master IDE Controller (http://bswd.com/idems100.pdf , which seems to be https://storage.googleapis.com/google-c ... ems100.pdf)) appear broken.
Trying to emulate a i440fx PIC IDE controller, I now know two things, from experience with how the BIOS configures it:
- Although an user named Giawa (https://wiki.osdev.org/index.php?title= ... &redlink=1 ) says that the controller I/O base address is at +0, this can only be at +2, because the I/O BARs of the PCI specification don't allow using bits 0 and 1 (https://en.wikipedia.org/wiki/PCI_configuration_space , bit 0 must be 1 to designate an I/O BAR and bit 1 is reserved, so it requires a 32-bit base I/O port alignment by design).
- Seeing as how the i430fx for example configures the PCI IDE controller of it's own motherboard, if found configurable (according to it's official documentation, interestingly enough, BAR4 exists, but BAR 0/1/2/3 isn't documented at all, probably non-existent and forced to 0 (doubleword), which isn't documented either (some BARs might be unimplemented on real chipsets and forced to 0 when that is the case). i430fx seems to use them to move ATA controllers, where somehow the second ATA controller can be moved up to the primary controller's I/O address (and the secondary I/O ports unused), seen from setting up the BIOS setup in different ways). usually it's the defaults however (1f0,3f0,170,370 for BARs 0-3, BAR4 is dynamically assigned depending on the hardware however (The IDE DMA registers' I/O ports)).
Anyone knows what the actual behaviour is on real PCI IDE controllers (whether onboard or plugin cards)?
Edit: Also, how does the command register bits affect legacy and PCI IDE port addresses, if at all for legacy? Does it disable the legacy I/O ports too?
Edit: Also, the bottom two links (PCI IDE Controller Specification (http://www.bswd.com/pciide.pdf , which seems to be https://www.isdaman.com/alsos/hardware/hdc/pciide.pdf) and Programming Interface for Bus Master IDE Controller (http://bswd.com/idems100.pdf , which seems to be https://storage.googleapis.com/google-c ... ems100.pdf)) appear broken.