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 Post subject: The TLB, caches and INVLPG instruction
PostPosted: Mon Oct 09, 2017 7:07 am 
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I can understand everything in virtual memory except the TLB and I can't find the purpose of the INVLPG instruction. Can someone explain it to me?
Also what is the caches and the caching?

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Last edited by ARISTOS on Mon Oct 09, 2017 7:13 am, edited 1 time in total.

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 Post subject: Re: The TLB and INVLPG instruction
PostPosted: Mon Oct 09, 2017 7:13 am 
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In essence, the goal of the TLB is simple: It is very expensive to do a full page adres lookup on every memory access, as that would lead to 3 memory reads for every memory access (assuming 32 bit 4K pagesize paging). The processing required for this would slow the processor down a lot. So instead of doing such a lookup on every memory read, the processor just remembers what previous outcomes were in a cache, the TLB. However, this means that on a memory read, it is no longer checking the actual page tables, so it won't notice if the software has made a change to them. The INVLPG instruction is basically a heads up to the processor, telling it that anything it assumed for the given adres based on past accesses is may have changed, and forcing it to check the page tables next time it needs that particular page.


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