Geri wrote:
zeitue wrote:
You claim your CPU is easy to emulate, what method do you plan to use to emulate it(dynamic translation, visualization, JIT, or some kind of a mix of methods)?
since subleq does not have multiple opcodes, there is no need for dynamic translation, or jit, since the code can be executed directly on the cpu/gpu using directly the cpu's/gpu's instruction set. maybe 2-5 clock per op is possible. i am not yet sure, since i not yet have tried it. basically, executing subleq instruction is:
mem[b]-=mem[a];
if(mem[b]<=0) eip=c;
(there is no need to dynamically compile x86 code from this, since its alreday native)
How can the X86 code run negatively on your platform when your platform is a different architecture all together?
The X86 is a CISC architecture and you said yours was URISC do you plan for a compatibility layer or is there something special I'm missing?
Geri wrote:
zeitue wrote:
Would this be usable in a bytecode virtual machine as the CPU of a process virtual machine?
this will be usable in any kind of virtual machine, emulator, including a full system emulator, or an user-mode-only bytecode that runs in -for example, in a game software, to process your strips.
also, the compiler will be able to create non-os binary that does not requires an operating system under it. the operating system's kernel will be compiled with this, and its able to compile itself too, so it will be hopefully self-hosting.
i will release the specifications of the platform and the virtual machine that requires to run it.
do you mean that the code will be like a dynamically expanding and changing?
If you manage this you could possibly produce features of an A.I. in your platform.
Geri wrote:
zeitue wrote:
How does this architecture preform as far as speed and power in comparison to the X86, Arm, Power PC, ....?
-since this architecture have large ,,instructions'', and requires a lot of operation sometimes, its approx 40-95% slower than a modern x86, arm, mips, or powerpc core, on the same clock speed. (depends on the algo). however, the alu and fpu of a modern 64 bit x86 or arm system requires around 100-200 million transistor per core, alu of this architecture requires only a few hundred of transistor.
-when counting 1 billion transistor for cache, we have room for ~5000 smp capable core with the current manufacturing technologies.
-when emulating, its much faster than emulating arm, x86 or mips.
-when we target extreme low power consumption, such like mobiles, tetrises, any kind of extreme-low-end chinese cpu manufacturer can build it for the same price like they current fixedfunction processors, on the same speed. and also, its easy to implement it in hardware
- Aren't large instructions a feature of the CISC architecture?
- So it's faster when running on platforms like ARM, MIPS, or X86? Or just in general?
- There are a lot of Chinese MIPS clones out there and they are usually used in $99 Laptops