Hello,
I need a short clarification, of how multibyte IO port accesses are handled on hardware level.
What does an
Code:
outw(port, data);
do exactly (assuming
data is an 16 bit variable)?
1.)
Code:
outb(port, LOBYTE(data));
outb(port, HIBYTE(data));
2.)
Code:
outb(port, LOBYTE(data));
outb(port+1, HIBYTE(data));
3.) Or does every single IO port has it's own size (0x70 is byte; 0xCF8 is dword and 0xCF9 to 0xCFB do not exist or maybe are anything completly different; ...) and it depends on the hardware connected to an IO port.
To understand the behaviour, I tried to read an word from port 0x70, assuming it will return the CMOS address (0x70) in AL and CMOS data (0x71) in AH but it returned 0xFFFF. (Of couse I set the CMOS address to a valid value before).
So I think 1.) and 2.) are wrong. But this differs from the text I read in the Intel manuals:
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture, 16.3 I/O ADDRESS SPACE, page 16-1 wrote:
Any two consecutive 8-bit ports can be treated as a 16-bit port, and any four consecutive ports can be a 32-bit port. In this manner, the processor can transfer 8, 16, or 32 bits to or from a device in the I/O address space. Like words in memory, 16-bit ports should be aligned to even addresses (0, 2, 4, ...) so that all 16 bits can be transferred in a single bus cycle. Likewise, 32-bit ports should be aligned to addresses that are multiples of four (0, 4, 8, ...). The processor supports data transfers to unaligned ports, but there is a performance penalty because one or more
extra bus cycle must be used.