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Digital logic design and simulation project
https://forum.osdev.org/viewtopic.php?f=13&t=31183		 Page 1 of 1
Author:  Peterbjornx [ Sun Jan 08, 2017 5:34 pm ]
Post subject:  Digital logic design and simulation project
Because of a project I am planning to start in the near future, I was looking for a good, modern, digital logic design suite that was
  • Free
  • Hackable
  • Powerful
I considered several options, but none of them were good enough. I looked at extending logisim but its total lack of documentation and weird design choices made this infeasible.
As a result of this I have started working on my own software for this purpose, I am planning to make it have at least these features:
  • Timing analysis
  • Data level signal inspection ( grouping buses and showing the actual value instead of 2^N high/low values )
  • Netlist export
  • Eurocard layout editor
  • Schematic entry

I have first started work on the circuit representation and simulator, the simulator is an event driven design which attempts to allow efficient, yet accurate modeling of large designs.

The project is written in Java, as it is an easy language for application development.

GitHub Project: https://github.com/peterbjornx/openlogiceda

Progress:
January 9, 2017 - First Simulator tests
A circuit with two clocks and an AND gate: ( notice the propagation delay ):
Image

January 12, 2017 - Working on the component symbol editor
Testing pin placement,
Functions already implemented: Undo/Redo, Copy, Delete, Move, Rotate, Add, Context menu, Select, Multiple select, Save, Open, Edit properties
Image
Author:  dchapiesky [ Mon Jan 09, 2017 12:52 pm ]
Post subject:  Re: Digital logic design and simulation project
A worthy undertaking! Good luck with it and keep us posted.

Do you have a maximum number of gates you envision it will be able to support?

I ask only because I had a simulation system (not electronics related) which became very useful - so much so that running multiple side-by-side comparisons became useful - and then one day none of them would fit in memory.

So when doing simulations I offer this advice - divorce the simulation from the GUI via networking and design the simulation to be scalable and parallel. While this seems overkill in the beginning, the ability to make a tweak to some sim code and run old and new versions against same data is invaluable.

Finally - since you are working with Java - I will recommend:

http://www.axonframework.org/

A CQRS (Command/Query Responsibility Separation) Framework and Event Store

Your sim event behavior code become discrete methods
Your sim event stream is recorded and can be played back (actually reducing run time)
Your sim event stream becomes accessible via a REST API so that you can hook in other sim applications to consume and generate additional events

It kicks @$$ and you work on the sim and not on the db

Cheers
Author:  Peterbjornx [ Wed Jan 11, 2017 7:30 pm ]
Post subject:  Re: Digital logic design and simulation project
Added a component editor ( see main post )
Author:  Peterbjornx [ Thu Jan 12, 2017 10:44 am ]
Post subject:  Re: Digital logic design and simulation project
Component editor is almost complete
Image
Author:  Peterbjornx [ Sun Jan 15, 2017 11:30 am ]
Post subject:  Re: Digital logic design and simulation project
Schematic editor and sim
Image
Author:  Ycep [ Sun Jan 15, 2017 12:58 pm ]
Post subject:  Re: Digital logic design and simulation project
You should make differences between compoments so users could spot a difference between resistor and capacitator.
Except that, it looks amazing!
Author:  Peterbjornx [ Sun Jan 15, 2017 8:35 pm ]
Post subject:  Re: Digital logic design and simulation project
Im not planning on supporting any analog components, but in fact, a component can be designed however the user likes: They are all just drawings similar to a schematic, fully customizable.
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